In the past, government agencies played pivotal roles in the development of new technologies. For example, Internet is an outgrowth of the ARPAnet project sponsored by the Defense Advanced Research Projects Agency (DARPA) of the United States government. Recently, consortia of private industries, often in cooperation with government agencies, have entered into this picture. As a consequence, researchers in academia have shifted their attentions much more towards real-world applications. In the panel discussion, we first compare the traditional roles of funding agencies in the USA, EU, and Asia. We then focus on the new trends in this funding business in each of the three regions. We will examine why and how such shifts have been made and discuss the roles of funding agencies to be played in the coming years. In particular, we will attempt to search for future roles and new forms/ways of the funding agencies from the viewpoint of economic development driven by technology advancement.

Summary form only given, as follows. Rapid growth in semiconductor technology has greatly changed the situation of research and development between companies from one of competition to collaboration. With so much cooperation between enterprises, what role, if any, should universities play? What do companies expect of universities? How and what do universities contribute to society ? In this session panelists will introduce the present status of collaboration between universities and industries in their respective countries and give their ideas toward a more effective cooperation system, Is it necessary to promote collaboration between universities and industry? The advantages to both sides in the collaboration between universities and industry will be discussed frankly.

This paper outlines the concepts and the key technologies for designing high-performance mainframe computers.The goals of the design automation system are:1) reducing the development period, 2) implementing high performance.We perceive that both of the goals must be achieved for the timely development of mairtframe computers that meet the market demand.The latest high-performance mainframe computer, the Hitachi M-880, was successfully designed by utilizing this system, and total capability of the system has been proven.

This paper describes the algorithm, implementation, and evaluation results of a new fault simulator called RFSIM, which is designed for combinational circuits. In order to accelerate fault simulation, two basic principles are introduced, a Detectable Fault Only (DFO) principle and a Candidate Gate Once (CGO) principle. The DFO principle is a dynamic reduction algorithm, which aims at drastically reducing computational complexity by utilizing blocking gate information. The CGO principle is an implementation technique which is utilized to implement the DFO principle effectively. Experimental results show that RFSIM is more than 10 times faster than a conventional concurrent fault simulator, and confirms that the DFO principle contributes to a drastic reduction in the number of faults to be simulated. A fault reduction ratio of around 25 to 1 was achieved in one of the benchmark circuits.

Placement algorithms optimizing signal delay as well as wirability for high-speed ECL masterslice LSI's are proposed. Equivalent constraints of wire length for clock skew, data path delay, and wired-OR are classified according to upper and lower limits. To maintain such limits, a top-down method utilizing an augmented two-dimensional clustering placement with “scope” and “zone”, which are new concepts representing limits, and an iterative weighted improvement method are presented. Such algorithms are applied to hundreds of 2 K and 5 K gate ECL masterslice LST's for a newly developed high-end mainframe computer, the Hitachi M-680H. Through such algorithms, the physical design is greatly improved by guaranteeing high wirability and improving electrical characteristics.

Routing algorithms for multi- (more than 3) sided pin arrangements are presented. These algorithms are essential for layouts mixing standard cells with custom macros such as ROM, RAM, PLA and ALU. An extended layout model in which these algorithms are applied is also presented. An experimental result regarding the effect on block area with respect to cell height, obtained by comparing an extended model with a traditional model, is described.