Interest in teaching-track faculty positions has been steadily increasing as enrollments in computer science degree programs continue to trend upward. While departments have welcomed these new teaching-track faculty members, senior faculty, department chairs, and university committees often struggle with how to best evaluate these faculty members during the promotion process. In our experience, some universities try to use a "watered-down" version of the tenure-track promotion standards with the intent of uniformity. Other universities have created whole new processes, which may be better at capturing the differences in teaching-track positions, but also can create a "second-class citizen" status for the teaching-track faculty members.

In recent work, we developed an educational module for undergraduate computing students, to bring inclusivity and engagement into the advanced cybersecurity education topic of stack smashing attacks and defenses. Our module comprises four guided learning activities, and an active learning exercise that integrates a stack smashing attack visualization tool, DISSAV, developed in prior work. The module was deployed in an undergraduate cybersecurity course across multiple semesters, showing favorable results. In the current work, we outline a plan to evaluate the effectiveness of the module for an underrepresented, underserved community in computing-neurodivergent students, specifically, students with Autism Spectrum Disorder (ASD) or Attention Deficit Hyperactivity Disorder (ADHD). We plan to deploy our module to participants recruited from the AccessComputing group, a cohort of about 600 computing students and recent graduates across the US who have disabilities such as ADHD and ASD. We will evaluate the effectiveness of our stack smashing module in terms of learning, engagement, and accessibility for neurodivergent students through multi-pronged data collection and a mixed-methods analysis. We will use insights from the study to refine our module and to establish guidelines for future course modules and activities, to better serve neurodivergent students while continuing to serve all computing students.

This innovative practice full paper describes a large-scale implementation and evaluation of an academic integrity module tailored for students in the Computer Science Program at the University of North Carolina at Charlotte. The module aims to educate students about academic misconduct, its consequences, and strategies to prevent it. While various approaches exist to tackle academic misconduct in computing, our approach is unique in two ways. First, it is a proactive approach that seeks to educate and empower students on this important topic, to help them be responsible for their actions in the academic setting, and be aware of the potential consequences they may face if they resort to academic integrity violations, rather than face potentially punitive consequences. Second, we incorporate scenarios and information that are specifically relevant to the Computing discipline throughout the module. This paper presents the module's design, outcomes from its large-scale deployment, student feedback on its effectiveness, and reasons students typically resort to academic integrity violations. Additionally, it discusses plans for continuous improvement based on student input and information about emerging tools and technologies (e.g., Artificial Intelligence powered tools). We expect that this paper will help guide the rapid adoption, deployment, and evaluation of such a program -specific academic integrity learning module at other institutions. We expect that our module itself can be adapted to other computing programs with only a small amount of effort.

This research-to-practice full paper describes our comparative analysis of two different project-based learning (PBL) practices to identify determinant factors in PBL that can motivate and enhance student learning. Project-based learning, a widely recognized form of experiential learning, employs the “learning by doing” approach to help students build concrete knowledge through hands-on experience. Numerous studies have demonstrated that this knowledge transformation process can significantly enhance students' critical thinking and problem-solving skills, while also boosting their motivation and engagement. However, there is a lack of research comparing different PBL practices to pinpoint the essential design elements that maximize student learning. Our study focuses on half-term long PBL practices in online undergraduate database classes with similar demographics, where except for the differences in project-based learning practices, all others in two sections were the same. We compare company-sponsored projects with student-selected projects to analyze how these different approaches impact student learning outcomes and what could be determinant factors influence student project-based learning. Student-selected project-based learning allows students to choose their own data domain of interest. Company-sponsored project-based learning grants students less freedom in topic selection but could provide students with opportunities to collaborate with company professionists and learn the real needs from industry and have a potential to secure an intern job, though there exists uncertainty and unpredictability in the collaboration. Both project-based learning practices vary in the following five characteristics that influence projects: (1) Centrality, (2) Driving question, (3) Constructive investigations, (4) Autonomy and (5) Realism. Our comparative analysis reflects the inherent variations in complexity and difficulty between the two types of PBL practices. We conducted two surveys to investigate student perceptions of their project experiences. We developed a web dashboard to conduct comparative analysis for a more general purpose. Through quantitative analysis of student performance and engagement time, as well as qualitative analysis of survey responses, we identify statistically significant determinants that influence the effectiveness of PBL. This study lays the groundwork for designing guidelines to facilitate effective project-based learning.

This Innovative Practice paper presents the design, deployment, and evaluation of a software security module that teaches stack smashing attacks and defenses using innovative pedagogical practices. Widely ubiquitous buffer overflow vul-nerabilities and stack smashing attacks that exploit them are critical components in advanced software security curricula, since buffer overflows can arise due to simple programmer oversight, and stack smashing can have dangerous consequences in critical systems. However, these topics are known to be difficult to teach and learn due to the vast amount of background needed, the difficulty of learning type-unsafe languages, and laborious memory address space calculations involved. In this work, we aim to bring innovative pedagogical practices to this advanced cybersecurity education topic through a suite of four guided learning activities that follow the Process Oriented Guided Inquiry Learning (POGIL) style, and DISSAV, an interactive visualization tool for modeling stack smashing attacks. This paper presents an evaluation of the module based on deploying it in multiple sections of an introductory undergraduate cybersecurity course in the UNC Charlotte in Fall 2022, Spring 2023, and Fall 2023. Our study finds that students have mostly positive perceptions about activity structure / design, content, and style, but that improvements may be needed to some aspects, including question phrasing, activity length, and teamwork facilitation.

In recent years, Academic Integrity (AI) cases in the Computer Science (CS) discipline are on the rise, with students often being unaware of what constitutes a violation and its potential consequences. This prompted us to develop an AI module that aims to educate CS undergraduate students to recognize misconduct in academic scenarios, their potential consequences, and recall strategies/resources to avoid misconduct in the CS context. We have deployed this module in eight CS courses in UNC Charlotte. In this poster, we present our motivation, design guidelines, deployment details, and the results of a study based on data collected in Spring and Fall 2021.

This paper presents Criminal Investigations, a gamified, scalable web-based framework for teaching and assessing Internet-of-Things (IoT) security skills. Criminal Investigations is packaged as a series of stackable IoT security activities; the current version uses React for the front-end development and Python for the back-end, and is deployed as a web application on a university server. Criminal Investigations promotes student engagement and learning by incorporating gamification concepts such as storytelling, experience points, just-in-time learning content delivery and checkpoints into activity design. This paper presents a pilot deployment of Criminal Investigations' first, fully-deployed, prototype activity "Reverse Engineering and Analyzing IoT Firmware''. The results of the pilot deployment indicate that Criminal Investigations provides an engaging, user-friendly, accessible environment, and helps students achieve the learning objectives of the prototype activity.

The COVID-19 pandemic led the majority of educational institutions to rapidly shift to primarily conducting courses through online, remote delivery. Across different institutions, the tools used for synchronous online course delivery varied. They included traditional video conferencing tools like Zoom, Google Meet, and WebEx as well as non-traditional tools like Gather.Town, Gatherly, and YoTribe. The main distinguishing characteristic of these nontraditional tools is their utilization of 2-D maps to create virtual meeting spaces that mimic real-world spaces.

This poster presents Criminal Investigations, a text-based interactive activity designed to teach and assess reverse-engineering and firmware analysis skills in upper-division undergraduate cybersecurity courses. The activity incorporates elements of game design such as storytelling, experience points (XP), and just-in-time learning content delivery to increase student engagement and learning. Criminal Investigations is implemented as an easily accessible web-based application, deployed in a cloud-based environment.

In this poster, we describe our research on the use of small units of content, termed minimal interventions, to create awareness of embedded systems security concepts in an undergraduate course, Introduction to Operating Systems and Networking. This work focuses on the incorporation of simple activities such as short readings, and the evaluation of their potential as teaching tools. To study the effectiveness of this minimal intervention approach, we collected student performance data over six (6) semesters and across multiple modalities of the course, with a total of 1,168 study participants. Students were asked to complete a short survey before and after completing the activities, to assess prior knowledge of the subject and measure knowledge gains that resulted from participation in the activity.

In this poster, we describe our experiences with improving student preparedness in a junior-level course, Introduction to Operating Systems and Networking, that is taught in multiple modalities. The course is designed around the use of Active Learning techniques and the face-to-face version uses the Flipped Classroom model. Course content, termed 'preparatory work', is delivered to students via lecture videos and online readings/tutorials. Students then engage with the course material via hands-on, application-oriented activities. One of the challenges we faced when we first 'flipped' this class is that students would not perform the necessary preparatory work before class. To address this issue, we explored the use of forcing functions, i.e., course design elements that help ensure the completion of preparatory work by students. We discuss the different forms of forcing functions that we used and present preliminary results on their effectiveness in improving preparedness.

Soft skills such as collaboration, communication and time management are essential to the success of computer science students both in school and after they enter the IT profession. While employers value these skills highly, there are so many technical skills to cover in computer science programs that these soft skills are not typically primary learning objectives for CS classes. As such, it is difficult to find time and space to address them directly. In this study, we investigate whether Classcraft, a game-based classroom behavior management platform designed for K-12 students, can motivate undergraduate students to develop their soft skills in large computing classes. To this end, we utilized Classcraft with 234 students across two face-to-face sections and one online section of an undergraduate "Introduction to Operating Systems and Networking" course to determine whether gamifying the engagement component of the course would motivate students to participate in co-curricular activities, enhance student collaboration and improve communication and time management. There were no in-game activities - the students in each section of the class earned experience points in Classcraft as a reward for completing class activities ahead of time, collaborative learning and teamwork, and asking or answering questions in class or via discussion forums in our learning management system. In this poster, we report our preliminary results of the impact of such a platform on student engagement in soft skills.

Growing processing demand on multitasking real-time systems can be met by employing scalable multicore architectures. For such environments, locking cache lines for hard real-time systems ensures timing predictability of data references and may lower worst-case execution time. This work studies the benefits of cache locking on massive multicore architectures with private caches in the context of hard real-time systems. In shared cache architectures, the cache is a single resource shared among all of the tasks. However, in scalable cache architectures with private caches, conflicts exist only among the tasks scheduled on one core. This calls for a cache-aware allocation of tasks onto cores. The objective of this work is to increase the predictability of memory accesses resolved by caches while reducing the number of cores for a given task set. This allows designers to reduce the footprint of their subsystem of real-time tasks and thereby cost, either by choosing a product with fewer cores as a target or to allow more subsystems to be co-located on a given fixed number of cores. Our work proposes a novel variant of the cache-unaware First Fit Decreasing (FFD) algorithm called Naive locked First Fit Decreasing (NFFD) policy. We propose two cache-aware static scheduling schemes: (a) Greedy First Fit Decreasing (GFFD) and (b) Colored First Fit Decreasing (CoFFD) for task sets where tasks do not have intratask conflicts among locked regions (Scenario A). NFFD is capable of scheduling high utilization task sets that FFD cannot schedule. Experiments also show that CoFFD consistently outperforms GFFD, resulting in a lower number of cores and lower system utilization. CoFFD reduces the number of core requirements by 30% to 60% compared to NFFD. For a more generic case where tasks have intratask conflicts, we split the task partitioning between two phases: task selection and task allocation (Scenario B). Instead of resolving conflicts at a global level, these algorithms resolve conflicts among regions while allocating a task onto a core and unlocking at region level instead of task level. We show that a combination of dynamic ordering (task selection) with Chaitin’s Coloring (task allocation) scheme reduces the number of cores required by up to 22% over a basic scheme (in a combination of monotone ordering and regional FFD). Regional unlocking allows this scheme to outperform CoFFD for medium utilization task sets from Scenario A. However, CoFFD performs better than any other scheme for high utilization task sets from Scenario A. Overall, this work is unique in considering the challenges of future multicore architectures for real-time systems and provides key insights into task partitioning and cache-locking mechanisms for architectures with private caches.

Software Managed Manycore (SMM) architectures -- in which each core has only a scratch pad memory (instead of caches), -- are a promising solution for scaling memory hierarchy to hundreds of cores. However, in these architectures, the code and data of the tasks mapped to the cores must be explicitly managed in the software by the compiler. State-of-the-art compiler techniques for SMM architectures require inter-procedural information and analysis. A call graph of the program does not have enough information, and Global CFG, i.e., combining all the control flow graphs of the program has too much information, and becomes too big. As a result, most new techniques have informally defined and used GCCFG (Global Call Control Flow Graph) -- a whole program representation which captures the control-flow as well as function call information in a succinct way -- to perform inter-procedural analysis. However, how to construct it has not been shown yet. We find that for several simple call and control flow graphs, constructing GCCFG is relatively straightforward, but there are several cases in common applications where unique graph transformation is needed in order to formally and correctly construct the GCCFG. This paper fills this gap, and develops graph transformations to allow the construction of GCCFG in (almost) all cases. Our experiments show that by using succinct representation (GCCFG) rather than elaborate representation (GlobalCFG), the compilation time of state-of-the-art code management technique [4] can be improved by an average of 5X, and that of stack management [20] can be improved by an average of 4X.

Cyber-Physical Systems (CPS) consist of computational components interconnected by computer networks that monitor and control switched physical entities interconnected by physical infrastructures. A fundamental challenge in the design and analysis of CPS is the lack of common semantics across the components. We address this challenge by employing a novel approach that composes the correctness of various components instead of their functionality using a conjunction of non-interfering logical invariants. We present a distributed algorithm that uses this approach to adaptively schedule power transfers between nodes in a smart power grid in such a way that the stability of both the computer network and the physical system are maintained. Simulation results demonstrate the necessity and usefulness of our approach in maintaining overall system stability in the presence of uncertainties in the computer network and with limited information about the global state of the system.

Providing a-priori temporal guarantees is paramount in real-time systems. Although much of the normal operation in such a system is modeled using sporadic tasks, event-driven behavior is modeled using aperiodic jobs. To ensure an acceptable Quality of Service for aperiodic jobs without jeopardizing safety of sporadic tasks, aperiodic servers were introduced. While aperiodic servers periodically reserve a quota for the execution of aperiodic jobs, they do not take into account, indirect cache-related delays that the execution of aperiodic jobs could impose on sporadic tasks, thereby making their use in systems with caches unsafe. In this paper, we introduce the concept of a Cache Delay Server to solve this problem for sporadic tasks (and thus, for periodic tasks). Every sporadic task is allocated a delay quota to accommodate the cache-related delay that could potentially be imposed due to aperiodic job execution. An aperiodic job is allowed to execute only when all active lower-priority sporadic jobs have sufficient delay quota to accommodate it. We also present a technique to calculate delay quotas for sporadic tasks within a given task set. Simulation results demonstrate that the use of a Cache Delay Server ensures safety of sporadic task execution in systems using caches while providing reasonable average-case response times to aperiodic jobs.

Locking cache lines in hard real-time systems is a common means to ensure timing predictability of data references and to lower bounds on worst-case execution time, especially in a multi-tasking environment. Growing processing demand on multi-tasking real-time systems can be met by employing scalable multi-core architectures, like the recently introduced tile-based architectures. This paper studies the use of cache locking on massive multi-core architectures with private caches in the context of hard real-time systems. In shared cache architectures, a single resource is shared among {\em all} the tasks. However, in scalable cache architectures with private caches, conflicts exist only among the tasks scheduled on one core. This calls for a cache-aware allocation of tasks onto cores. Our work extends the cache-unaware First Fit Decreasing (FFD) algorithm with a Naive locked First Fit Decreasing (NFFD) policy. We further propose two cache-aware static scheduling schemes: (1) Greedy First Fit Decreasing (GFFD) and (2) Colored First Fit Decreasing (CoFFD). This work contributes an adaptation of these algorithms for conflict resolution of partially locked regions. Experiments indicate that NFFD is capable of scheduling high utilization task sets that FFD cannot schedule. Experiments also show that CoFFD consistently outperforms GFFD resulting in lower number of cores and lower system utilization. CoFFD reduces the number of core requirements from 30% to 60% compared to NFFD. With partial locking, the number of cores in some cases is reduced by almost 50% with an increase in system utilization of 10%. Overall, this work is unique in considering the challenges of future multi-core architectures for real-time systems and provides key insights into task partitioning with locked caches for architectures with private caches.

As real-time embedded systems integrate more and more functionality, they are demanding increasing amounts of computational power that can only be met by deploying multicore architectures. The use of multicore architectures with on-chip memory hierarchies and shared communication infrastructure in the context of real-time systems poses several challenges for task scheduling. In this paper, we present a predictable semi-partitioned strategy for scheduling a set of independent hard-real-time tasks on homogeneous multicore platforms using cache locking and locked cache migration. Semipartitioned scheduling strategies form a middle ground between the two extreme approaches, namely global and partitioned scheduling. By making most tasks non-migrating (partitioned), runtime migration overhead is minimized. On the other hand, by allowing some tasks to migrate among cores, schedulability of task sets may be improved. Simulation results demonstrate the effectiveness of our approach in improving task set schedulability over purely partitioned approaches while maintaining real-time predictability of migrating tasks. In our simulations, we achieve an average increase in utilization of 37.31% and an average increase in density of 81.36% compared to purely partitioned task allocation.

Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised.

Data caches are an increasingly important architectural feature in most modern computer systems. They help bridge the gap between processor speeds and memory access times. One inherent difficulty of using data caches in a real-time system is the unpredictability of memory accesses, which makes it difficult to calculate worst-case execution times (WCETs) of real-time tasks. While cache analysis for single real-time tasks has been the focus of much research in the past, bounding the preemption delay in a multitask preemptive environment is a challenging problem, particularly for data caches. This article makes multiple contributions in the context of independent, periodic tasks with deadlines less than or equal to their periods executing on a single processor. 1) For every task, we derive data cache reference patterns for all scalar and nonscalar references. These patterns are used to derive an upper bound on the WCET of real-time tasks. 2) We show that, when considering cache preemption effects, the critical instant does not occur upon simultaneous release of all tasks. We provide results for task sets with phase differences to prove our claim. 3) We develop a method to calculate tight upper bounds on the maximum number of possible preemptions for each job of a task and, considering the worst-case placement of these preemption points, derive a much tighter bound on its WCET. We provide results using both static-and dynamic-priority schemes. Our results show significant improvements in the bounds derived. We achieve up to an order of magnitude improvement over two prior methods and up to half an order of magnitude over a third prior method for the number of preemptions , the WCET and the response time of a task. Consideration of the best-case and worst-case execution times of higher-priority jobs enables these improvements.

Multicores are becoming ubiquitous, not only in general-purpose but also embedded computing. This trend is a reflexion of contemporary embedded applications posing steadily increasing demands in processing power. On such platforms, prediction of timing behavior to ensure that deadlines of real-time tasks can be met is becoming increasingly difficult. While real-time multicore scheduling approaches help to assure deadlines based on firm theoretical properties, their reliance on task migration poses a significant challenge to timing predictability in practice. Task migration actually (a) reduces timing predictability for contemporary multicores due to cache warm-up overheads while (b) increasing traffic on the network-on-chip (NoC) interconnect.This paper puts forth a fundamentally new approach to increase the timing predictability of multicore architectures aimed at task migration in embedded environments. A task migration between two cores imposes cache warm-up overheads on the migration target, which can lead to missed deadlines for tight real-time schedules. We propose novel micro-architectural support to migrate cache lines. Our scheme shows dramatically increased predictability in the presence of cross-core migration.Experimental results for schedules demonstrate that our scheme enables real-time tasks to meet their deadlines in the presence of task migration. Our results illustrate that increases in execution time due to migration is reduced by our scheme to levels that may prevent deadline misses of real-time tasks that would otherwise occur. Our mechanism imposes an overhead at a fraction of the task's execution time, yet this overhead can be steered to fill idle slots in the schedule, i.e., it does not contribute to the execution time of the migrated task. Overall, our novel migration scheme provides a unique mechanism capable of significantly increasing timing predictability in the wake of task migration.

Schedulability theory in real-time systems requires prior knowledge of the worst-case execution time (WCET) of every task in the system. One method to determine the WCET is known as static timing analysis. Determination of the priorities among tasks in such a system requires a scheduling policy, which could be either preemptive or non-preemptive. While static timing analysis and data cache analysis are simplified by using a fully non-preemptive scheduling policy, it results in decreased schedulability. In prior work, a methodology was proposed to bound the data-cache related delay for real-time tasks that, beside having anon-preemptive region (critical section), can otherwise be scheduled preemptively. While the prior approach improves schedulability in comparison to fully non-preemptive methods, it is still conservative in its approach due to its fundamental assumption that a task executing in a critical section may not be preempted by any other task. In this paper, we propose a methodology that incorporates resource sharing policies such as the priority inheritance protocol (PIP) into the calculation of data-cache related delay. In this approach, access to shared resources, which is the primary reason for critical sections within tasks, is controlled by the resource sharing policy. In addition to maintaining correctness of access, such policies strive to limit resource access conflicts, thereby improving the responsiveness of tasks.To the best of our knowledge, this is the first framework that integrates data-cache related delay calculations with resource sharing policies in the context of real-time systems.

Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a scheduling policy that determines priorities among tasks. Such policies can be non-preemptive or preemptive. While the former reduces analysis complexity and overhead in implementation, the latter provides increased flexibility in terms of schedulability for higher utilizations of arbitrary task sets. In practice, tasks often have non-preemptive regions but are otherwise scheduled preemptively. To bound the WCET of tasks, architectural features have to be considered in the context of a scheduling scheme. In particular, preemption affects caches, which can be modeled by bounding the cache-related preemption delay (CRPD) of a task. In this paper, we propose a framework that provides safe and tight bounds of the data-cache related preemption delay (D-CRPD), the WCET and the worst-case response times, not just for homogeneous tasks under fully preemptive or fully non-preemptive systems, but for tasks with a non-preemptive region. By retaining the option of preemption where legal, task sets become schedulable that might otherwise not be. Yet, by requiring a region within a task to be non-preemptive, correctness is ensured in terms of arbitration of access to shared resources. Experimental results confirm an increase in schedulability of a task set with non- preemptive regions over an equivalent task set where only those tasks with non-preemptive regions are scheduled non- preemptively altogether. Quantitative results further indicate that D-CRPD bounds and response-time bounds comparable to task sets with fully non-preemptive tasks can be retained in the presence of short non-preemptive regions. To the best of our knowledge, this is the first framework that performs D-CRPD calculations in a system for tasks with a non-preemptive region.

Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timing predictability of single real-time tasks has been the focus of much research, bounding the overhead of cache warm-ups after preemptions remains a challenging problem, particularly for data caches. This paper makes multiple contributions. 1) We bound the penalty of cache interference for real-time tasks by providing accurate predictions of data cache behavior across preemptions, including instruction cache and pipeline effects. We show that, when considering cache preemption, the critical instant does not occur upon simultaneous release of all tasks. 2) We develop analysis methods to calculate upper bounds on the number of possible preemption points for each job of a task. To make these bounds tight, we consider the entire range between the best-case and worst-case execution times (BCET and WCET) of higher priority jobs. The effects of cache interference are integrated into the WCET calculations by using a feedback mechanism to interact with a static timing analyzer. Significant improvements in tightening bounds of up to an order of magnitude over two prior methods and up to half a magnitude over a third prior method are obtained by experiments for (a) the number of preemptions, (b) the WCET and (c) the response time of a task. Overall, this work contributes by calculating the worst-case preemption delay under consideration of data caches

While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and particularly data caches) limit the timing predictability for data accesses that may reside in memory or in cache. This is a significant problem for real-time systems. The objective our work is to provide accurate predictions of data cache behavior of scalar and nonscalar references whose reference patterns are known at compile time. Such knowledge about cache behavior provides the basis for significant improvements in bounding the worst-case execution time (WCET) of real-time programs, particularly for hard-to-analyze data caches. We exploit the power of the cache miss equations (CME) framework but lift a number of limitations of traditional CME to generalize the analysis to more arbitrary programs. We further devised a transformation, coined "forced" loop fusion, which facilitates the analysis across sequential loops. Our contributions result in exact data cache reference patterns minus; in contrast to approximate cache miss behavior of prior work. Experimental results indicate improvements on the accuracy of worst-case data cache behavior up to two orders of magnitude over the original approach. In fact, our results closely bound and sometimes even exactly match those obtained by trace-driven simulation for worst-case inputs. The resulting WCET bounds of timing analysis confirm these findings in terms of providing tight bounds. Overall, our contributions lift analytical approaches to predict data cache behavior to a level suitable for efficient static timing analysis and, subsequently, real-time schedulability of tasks with predictable WCET.