In this paper we present the specification backpropagation technique which enables one to derive the constraint of an internal functional block with respect to a given DC specification for an analog/mixed-signal system. Based on this technique, we implement an efficient fault simulator which reduces the required efforts by (1) removing undetectable faults from the fault list, and (2) performing fault simulation only locally for the fault block. Simulation results on an industrial design show a speedup factor of 7.2 with 98% correct classification of detected and undetected faults as compared with full-chip DC fault simulation.

In this paper we propose an efficient fault macromodeling technique for analog/mixed-signal circuits. We formulate the fault macromodeling problem as a problem of deriving the macro parameter set B based on the performance parameter set P of the transistor-level faulty circuit. The fault macromodel is intended to be used for efficient macro-level fault simulation. In such applications, a common approach to speeding up the macromodeling process is to generate a large number of data pairs (P, B) (the training set) and interpolate an empirical mapping function B=F(P) based on the training set. In our technique, generation of each data pair requires only one run of macro-level simulation, as opposed to multiple runs of macro-level simulation required by iterative fault macromodeling techniques. We also propose a cross-correlation-based technique to select a subset of parameters from the high dimensional parameter set P to speed up function interpolation. We demonstrate the effectiveness and efficiency of our proposed fault macromodeling technique by showing some preliminary, experimental results on an industrial design.

In this paper, we propose a pseudorandom testing scheme for mixed-signal circuits. We first describe the pseudorandom testing technique for linear analog components and converters in mixed-signal circuits. With proper arithmetic operations on the responses to the random patterns, the impulse response of the device under test (DUT) can be constructed and used as the signature. By checking the constructed signatures against the derived tolerance ranges, we can infer the correctness of the DUT without explicitly measuring the original performance parameters. We also describe a technique of mapping the tolerance ranges in the performance space to its associated tolerance ranges in the signature space. The major advantages of our pseudorandom testing scheme are: (1) a universal input stimulus (white noise) is used and thus test generation can be avoided, (2) signatures for high quality testing can be easily constructed and thus testing cost can be minimized, and (3) the scheme can be used for Built-In Self-Test (BIST) implementation for DSP-based mixed-signal designs. We present simulation results to illustrate the effectiveness of the scheme.

We propose an efficient approach to functional testing for linear time-invariant (LTI) analog circuits. By using proper signatures (impulse response samples) to infer the satisfaction/violation of the specifications for the performance parameters (we call such a procedure implicit functional testing), we can achieve over 90% fault and yield coverages based on only a small number of signatures. We use the pseudo-random technique to estimate the impulse response samples. Our approach is effective in terms of costs of test equipments and production testing time. We also present simulation results to illustrate the effects of the randomness of the estimated impulse response samples on the fault and yield coverages.

In this paper, we address the problem of functional testing of mixed-signal circuits using pseudo-random patterns. By embedding the linear, time-invariant (LTI) analog circuit between a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), we can model the analog and converter circuitry as a digital LTI system and test it using the pseudo-random vectors. We give mathematical analysis and formulate the pseudo-random testing process as the linear transformation of a random process by the analog LTI device under test (DUT). We choose the first and the second moments of the transformed random process, which are closely related to the functionality of the DUT, as the signatures for fault detection. We show that such signatures can be estimated by proper arithmetic operations on the output responses of the DUT to the vectors generated by LFSRs. We illustrate and compare the effectiveness of several possible choices of signatures through analysis and experimental results of several circuits, in terms of their fault detection capabilities and the testing hardware requirements.

In this paper, a comprehensive macromodel for transistor level faults in an operational amplifier is developed. With the observation that faulty behavior at output may result from interfacing error in addition to the faulty component, parameters associated with input and output characteristics are incorporated. Test generation and fault classification are addressed for stand-alone opamps. A high fault coverage is achieved by a proposed testing strategy. Transistor level short/bridging faults are analyzed and classified into catastrophic faults and parametric faults. Based on the macromodels for parametric faults, fault simulation is performed for an active filter. We found many parametric faults in the active filter cannot be detected by traditional functional testing. A DFT scheme alone with a current testing strategy to improve fault coverage is proposed.