This paper presents a technique to study and estimate the dc performance of lateral power MOSFET switches used in on-chip dc-dc converters. The dc performance is characterized by the on-resistance and current distribution profile in the switch layout. In the proposed approach, a netlist is generated that consists of the parasitic resistances extracted from the metal interconnects along with the MOS device fingers present in the layout. This approach is modular and exploits repetitive patterns of power MOSFET layouts to expedite the extraction process. The extracted resistance values are computed from the geometrical and technological parameters of the metal polygons without the requirement of solving complex electromagnetic (EM) field equations. Comparison of results with an industry standard EM solver tool as well as experimental measurements amply demonstrates the computational efficiency and accuracy of the approach.

This paper presents the extensions and experimental validations of a new approach recently developed by the authors for accurate estimation of on-resistance (RDS(on)) of large lateral power MOSFET switch layouts present in on-chip DC-DC converters. This approach exploits the highly symmetric and repetitive patterns of power MOSFET layouts to generate the extracted resistance netlist efficiently resulting significant speed up in resistance extraction process. The extracted resistance values in the interconnects are computed from the metal geometry using models that relate resistance values to the geometric parameters of the layout. Comparison of results with an industry standard EM solver tool as well as experimental measurements for power MOSFET layouts of W/L ratio 105amply demonstrate the computational efficiency and accuracy of the approach establishing its applicability for industrial on-chip power array implementations.