Modular addition is a fundamental operation in public-key cryptographic algorithms operating in finite fields, such as elliptic curve cryptography (ECC), Chebyshev polynomials, and post-quantum cryptography (PQC). The performance of these cryptographic algorithms is limited by the conventional modular adder approach, which incorporates two cascaded adders in series. This approach leads to a doubled critical path delay, ultimately causing a decrease in frequency despite utilizing a high-performance adder. This research presents a high-performance, low-area architecture for a modular adder, employing a novel approach. Specifically designed for various prime fields recommended in public key cryptography, the architecture optimally utilizes the carry chain and exploits the structural advantages of the 7-series field programmable gate array and series beyond. Implementation results demonstrate superior performance, achieving operating frequencies of 290.0 MHz for 192 bits and 205.5 MHz for 1024 bits. Notably, the proposed design performs modular addition in a single clock cycle, resulting in an approximate 57% frequency enhancement compared to the conventional approach. Consequently, this architecture stands as an optimal solution for systems demanding high-speed operations.

Abstract The aim of this article is to design a new telehealth system with secured wireless transmission and classification of multiple biosignals using e‐Health sensors platform and Xbee modules with Arduino Uno and Raspberry Pi as acquisition and processing units, respectively. The collected data, such as temperature, airflow, position, Galvanic skin response and oxygen in the blood can be evaluated in order to monitor patient health state using threshold detection. The prediction of the cardiac state based on automatic identification of arrhythmias is validated by the classification of ElectroCardioGram (ECG) signals using Artificial Intelligence (AI) by exploiting TensorFlow and Keras tools. Different AI algorithms and a combination with different Machine Learning (ML) basing to transfer learning approach are tested. These algorithms include Artificial Neural Network (ANN), Convolutional Neural Network (CNN), Support Vector Machine (SVM), K‐Nearest Neighbour (KNN) and Random Forest (RF). At first, ANN and CNN are used to classify ECG‐scalogram images using softmax, then the used CNN model (VGG16) is employed to extract features and pass them to other traditional classifiers (SVM, KNN and RF) allowing to evaluate and select the best classifier, such that the ECG signal can be classified into four categories namely Normal Sinus Rhythm (NSR), Atrial Fibrillation (AF), Congestive Heart Failure (CHF) and other cardiac arrhythmia (ARR). The proposed method has been evaluated using real recorded signals and four PhysioNet databases. A Graphical User Interface (GUI) has been designed with C# under Visual Studio IDE allowing to display the results using personal computer (PC) or a network linked phone, which makes it possible to transfer the diagnosis with the prediction results to a remote clinic control room as Internet of Things (IoT) system application. The best classification accuracy of 99.56% is attained, confirming that the designed system allows a good trade‐off between low cost and performances in addition, it is easy to use with quick access to multiple biosignals. It has improved vital characteristics monitoring and diagnosis services quality under a robust secured wireless transmission using lightweight chaos‐based algorithm, thus preventing loss of life during critical health situations.

Cognitive radio (CR) technology is getting extensive attention to eliminate the problem of spectrum scarcity. This technology is based on Software Defined Radio (SDR) and some integrated intelligent functions such as spectrum sensing. This function is one of the crucial elements and its hardware implementation is important for the practical realization of the CR. This paper presents experimental results of the hardware implementation of the Goodness of Fit (GoF) based sensing for CR. Universal Software Radio Peripheral platform (USRP) is used for the experiments conducted. The choice of GoF based sensing for detecting spectrum holes is motivated by the advantage of requiring fewer samples to achieve the same sensing performance compared to Energy Detector (ED). Besides, the analytical expressions for the theoretical detection performance are derived. Computer simulations are carried out to evaluate the impact of fading channels on GoF based sensing. Numerical results confirm that the proposed GoF based sensing method outperform ED under fading channels. Furthermore, theoretical results of GoF based spectrum sensing are validated experimentally taking into account some parameters such as sample rate and sensing time. Finally, several scenarios of wideband GoF based sensing are considered to demonstrate the strengths of the considered method.

Context‐based adaptive binary arithmetic coding (CABAC) is a single operation mode for entropy coding in the last video coding standard high‐efficiency video coding. For high‐resolution applications, the throughput of one bin/cycle is not sufficient and it is a very challenging task to implement pipeline and/or parallel CABAC decoding architecture by simply adding more stages. Indeed, the tight data dependencies make it difficult to parallelise and cause it to be a throughput bottleneck for video decoding. Consequently, in order to improve the CABAC decoder throughput, parallel and pipeline architectures are used in authors’ design. In this work, an algorithm‐architecture adequation is proposed to implement a CABAC decoder on a field programmable gate array. Mainly, a new classification of 32 syntax elements is given to speed up the authors’ solution. Furthermore, the context selection and modelling of regular syntax elements are studied, designed and implemented. Finally, a novel technique of memories rearrangement to reduce the critical path delay required to process each binary symbol is proposed. As a result, the implementation can process 2.2 bins/cycle when operated at 123.49 MHz and exhibits an improved high‐throughput of 271.678 Mbins/s. The hardware architecture is coded using hardware description language and synthesised using ISE Xilinx tools targeting the Virtex4 platform.

In this paper, a new design approach based on chaotic encryption technique and System on Programmable Chip SoPC to protect fingerprint templates against some attacks is presented. This approach is based on the co-design methodology hardware/software (HW/SW) performed by using Xilinx FPGA platform. The proposed stream cipher algorithm is based on chaotic sequences of the Lorenz system. Simulation and experimental results clearly demonstrate that the proposed approach for protecting biometric authentication system provide a good trade-off between security and performance requirements in terms of efficiency and cost. This system could therefore be integrated into a real time secure access control system.

Spectrum sensing (SS) plays a significant role in cognitive radio network. In this paper, we present FPGA architecture implementation of Energy Detection (ED) based spectrum sensing and Goodness of Fit (GoF) based spectrum sensing methods. The aim of these methods is to detect the presence of signal in cognitive radio network (CRN) environment. These techniques have been described inVHDLand implemented on XilinxFPGAtechnology, through an experimental demonstration via a bench composed of dongle (RTL2832U), a laptop and aXUP Virtex-II Pro FPGAplatform. Implementation results and performance evaluation validate and demonstrate the feasibility of our hardware design. Therefore, this implementation confirms the efficiency (performance and complexity) of blind detection methods for cognitive radio. The results showed that the hardware performances matched well with theoretical analysis.

In this paper, a new algorithm combined compression and image encryption is presented. The proposed algorithm can be used in the field of high-speed confidential data transmission where security is required. The compression is based on a hierarchical structure called SPIHT(Set Partitioning in Hierarchical Trees). This compression is followed by an encryption scheme PSCS (Parametric Switching Chaotic System). The performances of this technique were evaluated in terms of compression quality and data security. Simulation results have shown the effectiveness of this technique, and thereafter, it is ready for a hardware implementation.

In this paper, we propose an interesting and original solution to the problem of chaotic synchronization which is focused in its high sensitivity to channel noise. We demonstrate through experimental design, the synchronization of tow embedded hyperchaotic Lorenz generators implemented separately in two FPGA circuits. The basic idea of the proposed solution consists of synchronizing two hyperchaotic systems without perturbing the hyperchaotic dynamic of the slave system. This means that, in an eventual wireless hyperchaotic communication system, whatever the perturbations suffered by the transmitted hyperchaotic carrier (drive signal) through the channel, our solution permits to generate an identical copy of the hyperchaotic carrier at the receiver and then recover the information signal correctly.