The recent surge in solar plant installations has notably decreased the reliance on fossil fuels while also presenting significant challenges to power grid. Therefore, the accurate forecasting of centralized and distributed solar power has become critically important. Although site-specific forecasting models typically perform better for utility-scale solar power plants, the model maintenance can be troublesome as the number of solar plants grows. Furthermore, the rapid growth and difficulties in real-time data collection associated with distributed solar systems exacerbate the complexity of regional gross solar power forecasting. To address these issues, we propose SolarMAE, a unified regional solar power forecasting framework enabling end-to-end precise forecasting for both centralized and distributed solar systems. It adopts masked autoencoder (MAE) pre-training strategy for numerical weather prediction (NWP) reconstruction at first, aiming to derive spatiotemporal correlations within meteorological variables, and then fine-tunes a temporal convolutional neural network which predicts future solar power generation. Experiments show that this framework outperforms state-of-the-art centralized or distributed solar power forecasting methods in accuracy, and significantly reduces model maintenance cost. It also demonstrates strong few-shot learning capabilities, which is particularly useful for the cold start problem of newly installed solar plants. The unified solar power forecasting system has been deployed in a province in eastern China, serving solar systems with over 73 GW gross installed capacity and more than 400 centralized solar plants.

In order to mitigate the high peak-to-average power ratio (PAPR) of the uplink waveform, the frequency domain spectrum shaping (FDSS) and $\frac{\pi }{2}$ BPSK modulation are adopted to DFT spread orthogonal frequency-division multiplexing (DFT-s-OFDM) for both data and pilot transmission in 5G new radio (NR). However, generating such pilot sequences with acceptable orthogonality and reduced PAPR causes a computationally intensive search. This paper introduces the constant envelope (CE) OFDM waveform for both pilot and data transmitting with a PAPR of 0dB. Especially, an modified channel estimation scheme with the optimized selection of modulation index is proposed to overcome the non-flat power spectral density caused by phase modulation in CE-OFDM. Numerical results prove the superiority of the proposed low-PAPR waveform over the classical NR signal in terms of both PAPR and BER performance.

Offset spatial modulation orthogonal frequency division multiplexing (OSM-OFDM) is demonstrated to offer a simple radio frequency (RF) switching structure with comparable bit error rate (BER) performance to conventional SM-OFDM. However, the OSM-OFDM waveform inherits the large peak-to-average power ratio (PAPR) of original OFDM, and suffers performance loss in terms of BER due to the nonlinear noise from high power amplifier (HPA). As a class of efficient PAPR reduction techniques, the BER performance of clipping-aided OSM-OFDM is first evaluated through theoretical analysis. Furthermore, in this contribution, we conceive a new antenna offset structure as grouped OSM-OFDM toward low PAPR, while its upper BER bound is quantified through theoretical analysis. Through simulation results, we demonstrate that compared to the original OSM-OFDM, both grouped OSM-OFDM and clipped OSM-OFDM are capable of striking a better balance between PAPR and BER performance, while the former one is without extra computational complexity and the later one needs distortion recovery at the receiver side.

In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

The Aggressive technology scaling makes modern advanced SRAMs more and more sensitive to soft errors that include single-node upsets (SNUs) and double-node upsets (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs. The cell mainly consists of six cross-coupled input-split inverters, constructing a large error-interceptive feedback loop to robustly retain stored values. Since the cell has many redundant storage nodes, the cell achieves the following robustness: (1) the cell can self-recover from all possible SNU; (2) the cell can self-recover from partial DNUs; (3) the cell can avoid the occurrence of other DNUs due to node-separation. Simulation results validate the excellent robustness of the proposed cell. Moreover, compared with the state-of-the-art typical existing hardened cells, the proposed cell achieves an approximate 61% read access time as well as 12% write access time reduction at the costs of 47% power dissipation as well as 44% silicon area on average.

This paper presents a single-event double-upset (SEDU) self-recoverable and single-event transient (SET) pulse filterable latch design for low power applications in 22nm CMOS technology. The latch mainly consists of eight mutually feeding back C-elements and a Schmitt trigger. Simulation results have demonstrated both the SEDU self-recoverability and SET pulse filterability for the latch using redundant silicon area. Using clock gating technology, the latch saves about 54.85% power dissipation on average compared with the up-to-date SEDU self-recoverable latch designs which are not SET pulse filterable at all.