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Mikhail S. Yenuchenko

dblp:241/1301 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0000-0002-5301-3871ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Interconnection networks and networks-on-chip · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.712023
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Integrated circuit design › analog and mixed-signal circuits
data converters
0.712023
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Interconnection networks and networks-on-chip › switching
switching scheme
0.712023
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

hierarchical chessboard flip · 0.7error profile rotation · 0.7
YearPublicationVenuePosition
2025 Hierarchical rotated binary placement for nonlinearity reduction in digital-to-analog converters
Mikhail M. Pilipko, Mikhail S. Yenuchenko
Integr.2
2023 Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs
abstract
This brief is devoted to the development of a switching scheme for unary digital-to-analog converters (DACs). Switching schemes are one of the possible solutions to compensate the influence of the component value deviations appearing during integrated circuit production. Previously known deterministic switching schemes have some weak points, which limit the compensation with resolution growth. In order to overcome such drawbacks, this work adapts the properties revealed and employed in switching schemes, where each element is split into several parts. Based on these properties, the novel hierarchical chessboard flip (HCF) switching scheme is proposed. The simulation demonstrated that HCF reduces the integral nonlinearity (INL) better than previously known solutions while being scalable to any even bit number in DAC array. Adoption to odd resolutions is also possible. Additionally, an extension of the commonly used simulation approach is introduced. Obtaining a dependence of INL reduction on the rotation angle of the error profile may reveal a weakness of some switching scheme in spite of competitive average values.
Mikhail M. Pilipko, Mikhail S. Yenuchenko
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2