Zheng-Hong Zhang

dblp:241/4310 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
delay-locked loop
0.412019
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop · DAC 2019
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design
0.412019
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop · DAC 2019

Methods — techniques the papers use, named apart from their topics

post-layout simulation · 0.4ping-pong delay line architecture · 0.4
YearPublicationVenuePosition
2019 The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop
abstract
The Tunable Delay Line (TDL) is the most important building block in a modern cell-based timing circuit such as Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL). In previously proposed TDLs, one dilemma exists -- they cannot be both power efficient and environmentally adaptive at the same time. In this paper, we present an effective solution for such a dilemma - a novel "ping-pong delay line" architecture. The idea is to use two small cell-based delay lines operated in a synergistic manner in the sense that they exchange the "role of command" dynamically like in a ping-pong game, and thereby jointly reacting to severe environmental changes over a very wide range. This proposed ping-pong delay line has been incorporated in a Delay-Locked Loop (DLL) design, to demonstrate its advantages by post-layout simulation.
Zheng-Hong Zhang, Shi-Yu Huang
DAC1