Binary polynomial multipliers impact the overall performance and cost of elliptic curve cryptography (ECC) systems. Multiplication algorithms with subquadratic computational complexity are widely used to reduce area requirements and improve the delay of ECC cryptographic hardware. This work presents an elliptic curve scalar point multiplication (SPM) processor implementation using a novel classification of improved overlap-free multipliers targeting applications in the Internet of Things (IoT) devices. The proposed multipliers combine the advantages of fewer partial products and the overlap-free reconstructions which results in better recurrence and improved performance. The proposed multipliers and point multiplication hardware were designed, implemented, and tested on FPGA. The implemented processor presents a reasonable trade-off between speed and area consumption, and the design compares favorably with the previous designs in terms of area-delay product.

Neuromorphic computers have been presented as alternatives to traditional von Neumann systems. Neuromorphic systems mimic neural structures of the human brain to make the energy-efficient and high-performance computations. This paper proposes high-speed with no DSP resources FPGA implementation of the SAM neuron model and its fully connected networks with random synaptic weights. The synthesis reports of the implemented SAM neuron with 50, 100, 500, 1000, 2000, 4000, 6000, and 8000 random inputs have been presented. Also, the results of the synthesized fully connected populations comprising 50, 100, 500, 1000, and 1500 SAM neurons have been reported. Accordingly, the FPGA synthesis results of the proposed spiking neuron and networks are noteworthy compared to the state of the arts in terms of performance and DSP resources.

A new and efficient Hodgkin–Huxley (HH) neuron has been implemented on field-programmable gate array (FPGA). Multiplication, division, and exponential terms were implemented using the COordinate Rotation DIgital Computer (CORDIC) algorithm with carefully selected iteration numbers for each operation to greatly reduce the hardware resource requirements while simultaneously maintaining system throughput and a maximum clock frequency of over 275 MHz. The proposed design achieves higher modeling accuracy than previously proposed designs and an accuracy-resource trade-off that represents dramatic improvements. Additionally, all the neuron’s physiological parameters are variable as inputs to the proposed design postimplementation for a high degree of freedom in neuroscientific simulations. The implemented neuron is presented with results, and the behavior of the implemented system is evaluated to verify its close behavioral matching to the target neuron model.

Novel binary polynomial multipliers have been designed using M-term overlap-free Karatsuba multiplication (OFKM), where$M$is 5–8. The proposed designs were realized in digital hardware and implemented on field-programmable gate array (FPGA) and the best value of$M$was selected and presented for common National Institute of Standards and Technology (NIST) operand sizes from 64 to 571 bits. The implemented hardware designs use a hybrid approach that combines a given M-term overlap-free Karatsuba multipliers with two-term splitting to reduce the need for zero-padding in the final recurrent stages. Compared to the traditional M-term Karatsuba multipliers, the proposed overlap-free implementations offer reductions in delay and area-delay product (ADP). The proposed designs also compare favorably to previous implementations of binary polynomial multipliers. Their favorable characteristics make the proposed overlap-free Karatsuba polynomial multipliers viable options for use in cryptographic systems where speed is a significant consideration and hardware resource consumption must be limited.

The concept of input sparsity in Spiking Neural Networks for pattern recognition is introduced and explored with the goals of reductions in network inference time and size, leading to lower resource requirements in hardware implementations. A method is proposed by which selective input sparsity can be inferred from the training set to reduce the size of the network before training and decrease the network inference time. This method also requires no additional pre-processing steps during the testing phase, making it an excellent candidate for edge applications. For a basic fully connected spiking neural network trained to solve the MNIST handwritten digits, selective input sparsity is applied and the network size is reduced by 58.16% and a 41.07% decrease in the network's inference time is observed without notable accuracy hinderance. In the case of the Fashion MNIST dataset, selective input sparsity reduced the network size by 55.99% and reduced the network's inference time by 59.05%.

In the above article[1], in the title of the article, the acronym FPGA was incorrectly used as FGPA. The correct title should be “An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation.”

Finite field multiplication is a fundamental and frequently used operation in various cryptographic circuits and systems. Because of its high complexity, this operation generally determines the overall complexity and cost of these systems. Therefore, finite field multipliers and their hardware implementation have received considerable attention from researchers. This article proposes a methodology to design an efficient Galois field multiplier. First, space and time complexities for theoretical and field-programmable gate array (FPGA) implementations of M-term Karatsuba-like finite field multipliers were obtained. In addition, an algorithm was developed to obtain an efficient design based on a composite M-term Karatsuba-like multiplier. Furthermore, the proposed multipliers were verified and implemented on various FPGA devices, and implementation results were presented. Reported device utilization and latency indicated that the proposed multiplier is roughly 26% faster and 15% more efficient in the area–delay product compared to the standard Karatsuba multiplier. Moreover, comparison with state of the art also indicated that the proposed design is leading in terms of effectiveness and speed.

Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area-delay product indicating the efficiency of design.

Spiking neurons, the models that mimic the biological cells in the brain, are described using ordinary differential equations. A common method to numerically solve these equations is Euler's method. An important factor that has a significant impact on the performance and cost of the hardware implementation or software simulation of spiking neural networks and yet its importance has been neglected in the published literature, is the time step in Euler's method. In this paper, first the Izhikevich neuron's accuracy as a function of the time step was measured. It was uncovered that the threshold time step that Izhikevich neuron becomes unstable is an exponential function of the input current. Software simulation performance, including total computational time and memory usage were compared for different time steps. Afterwards, the model was synthesized and implemented on the Filed Programmable Gate Array (FPGA). Hardware performance metrics such as speed, area and power consumption were measured for each time step. Results indicated that time step has a negative linear effect on the performance. It was concluded that by determining maximum input current to the neuron, larger time steps comparable to those used in the previous works could be employed.

Summary form only given. This paper proposes a neuromorphic platform for on-FPGA online Spike Timing Dependant Plasticity (STDP) learning, based on the COordinate Rotation DIgital Computer (CORDIC) algorithms. The implemented platform comprises two main components. First, the Izhikevich neuron model is modified for implementation using the CORDIC algorithm, simulated to ensure the model accuracy, described as hardware, and implemented on FPGA. Second, the STDP learning algorithm is adapted and optimized using the CORDIC method, synthesized for hardware, and implemented to perform on-FPGA online learning on a network of CORDIC Izhikevich neurons to demonstrate competitive Hebbian learning. The implementation results are compared with the original model and state-of-the-art to verify accuracy, effectiveness, and higher speed of the system. These comparisons confirm that the proposed neuromorphic system offers better performance and higher accuracy while being straightforward to implement and suitable to scale.