Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with$n$qubits requires$2^{n+4}$bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.

We propose an autonomous vehicle controlled by FPGAs. In our design, considering embedded systems, we apply the binarized neural networks (BNNs) which can realize a satisfying result in high speed and accuracy to recognize pedestrians and some obstacles on a given road. To detect the traffic light, a passive camera-based pipeline is applied. Furthermore, the implementation of road lane detection is based on color selection algorithm, Canny Edge Detection, and Hough Transformation. The proposed design is realized by two Xilinx boards: PYNQ-Z1 and Zynq-Xc7Z010. These two FPGA boards cooperate with each other through a shared network cable. In the proposed design, the resource used by Zynq-Xc7Z010 can be greatly reduced and the inference time on the FPGA has been thousands times faster than the software implementation.