Effect-Cause diagnosis procedures are used to diagnose failing dies and improve manufacturing yield. Several methods have been proposed to accelerate Effect-Cause diagnosis procedures by utilizing a small-sized fault signature dictionary. Recently, pre-silicon diagnosis simulation has been proposed to identify quality issues in diagnosis before silicon volume production. Asymmetric Partition Trees (APT) have been proposed to extract useful information in the fault dictionary for diagnosis simulation applications. APT has proven to have a minimum tree size. In this paper, we propose using fault group information in APT to distribute the fault signature dictionary across APT tree nodes. With APT, the small fault signature dictionary can be further reduced, thereby improving diagnosis performance. The larger the designs, the greater the savings.

Diagnosis simulation based on stuck-at faults cannot expose all chain diagnosis problems because silicon defects don’t behave exactly as stuck-at faults. For chain failures, the fault effect can be activated during scan shift cycles and capture cycles in scan test patterns. The activation conditions of silicon defects are generally more complex and do not activate the fault effect in all cycles. To accurately estimate diagnosis coverage during chain diagnosis simulation, this paper proposes using distinguishing bits. Distinguishing bits, which are simulation-failing bits of one fault but not simulation-failing bits of another fault, are used in this paper to distinguish each silicon defect from others. The chain diagnosis quality of silicon defects can be improved by increasing the distinguishing bits of all scan cell faults. Specific diagnosis test patterns are proposed to increase the number of distinguishing bits of each fault. If the diagnosis test patterns cannot be created, adaptive diagnosis points are proposed to modify the designs to facilitate the creation of these diagnosis test patterns.

As process geometry shrinks, the complexity of transistors in electrical devices have also increased exponentially. Silicon devices manufactured with these new processes are used in safety-sensitive products. Reliability is, therefore, an extremely important factor in such devices. High quality test and screening are a requirement during production of such devices. In this paper, we present a new methodology for advanced nodes like 3nm that include high quality test patterns to improve screening of defective parts and, scan diagnosis to achieve improved physical failure analysis resolution. In particular, the new scan diagnosis methodology presented in this paper improved defect identification especially in global control signal networks over previous techniques. Experimental results shown in the paper demonstrates the uncovering of real systematic defects that were encountered in silicon production at Samsung Foundry.

Diagnosis of defects on scan chains is the established methodology for improving semiconductor manufacturing yield throughout the production cycle. The best possible result is to obtain a perfect diagnosis resolution, i.e. identifying a single scan cell per defect. With increased structural complexity and emergence of new production technologies, like backside power, there is a need to improve diagnosis callout beyond single-cell to include transistor-level visibility. In this paper we will present a novel end-to-end software-based methodology for enhancing scan chain diagnosis resolution with cell aware information. The new diagnosis methodology enables the isolation of defects in control signals local to multi-bit register arrays. Volume diagnosis benchmarks and silicon data will be shown to present suspect area improvements that will allow for faster physical failure analysis (PFA) turnaround times.

A pre-silicon design-for-diagnosis flow is a critical step in IC manufacturing. It is the key to achieving high diagnosis quality, which is necessary to improve yield and meet time-to-volume business requirements. This paper introduces a novel mechanism that significantly enhances this process. By inserting an XOR gate at scan cells, we enable these cells to operate in an additional mode, thereby improving their diagnosability. The activation of this extra mode is facilitated by a combination of a diagnosis-enable signal bit and the scan-enable signal. A key aspect of our approach is using a local scan cell without an additional input pin to provide the diagnosis-enable signal, a practical innovation that enhances the efficiency of the manufacturing process.

Scan diagnosis has long been relied upon to provide localized defect suspects for a failing die using failing test cycle information for that die and design data. These suspects from scan diagnosis have been used to drive failure analysis (FA) to find the root cause of manufacturing yield loss. The fewer suspects that scan diagnosis produces (higher diagnosis resolution), the quicker and more efficient the FA cycle time. The gains observed are mainly due to the reduced need for fault isolation for these highly resolved diagnosis reports. Identifying design or test pattern related bottlenecks to diagnosis resolution earlier in the design cycle can be useful to anticipate the impact of a particular design on yield learning. In the technique described in this paper, we show how diagnosis resolution can be estimated from design data for both chain and logic defects. The detailed comparison of diagnostic metrics and resolution statistics from simulation and silicon results are presented. Overall, we observe strong correlation in the predicted resolution metrics and diagnosis quality.

Modern semiconductor chips contain a significant amount of area dedicated to global control and clock circuitry. Therefore, the manufacturing of such designs at a very high scale can potentially result in defects in said circuitry. Such defects can lead to multiple simultaneous scan chain failures and were previously omitted in volume yield learning efforts, primarily due to the lack of effective diagnosis methods. In this paper, we will present a novel methodology that provides diagnosis of control and clock network defects in volume environments. We present evaluation results using advanced node silicon data and failure analysis that successfully localized clock defects on advanced node production chips.

Reversible scan chain is an architecture targeted towards improving the quality of chain diagnosis. In this scan architecture, chains are designed to shift the test data in both directions to isolate a defect. We implemented this technique on a test chip in one of the most advanced technology nodes to measure its benefit over its cost. Test chips are typically low in volume and may suffer from worse diagnosis resolution and lower diagnosis convergence than production chips due to early process technology. Hence, it is very important to enhance diagnosis resolution and increase successful diagnosis data volume without losing accuracy to help expedite yield learning. In this paper, the detailed evaluation method together with silicon data and failure analysis results are presented. Moreover, we utilize this novel methodology for improving diagnostics suspect resolution and physical area. Overall, we observe significant benefit in diagnosis quality. Specifically, 4X improvement in the number of suspects and up to 7X improvement in suspect cell area is observed without losing accuracy. Design overhead is also presented and discussed.

Diagnosis becomes a much more prevalent factor in the successful fabrication process of a design. In order to keep up with continuously shrinking technology nodes, compression along with compaction techniques became a standard methodology allowing to control the cost of test. Typically compaction techniques focus on detectability thus maintaining high quality of test, but neglect or, in many cases, ignore their impact on diagnosis. This paper presents a compactor which allows significantly improving chain diagnosis resolution while maintaining high quality standards from detectability point of view and having virtually no impact on test time and logic diagnosis. The paper presents the X-press compactor which is driven in a way allowing to maximize diagnostic ability of chain failures. Specifically, the number of physical failure analysis-ready cases increased up to two times. The feasibility and efficiency of the proposed solution is confirmed by a number of experimental results performed for industrial designs, including actual chain diagnosis.

The following topics are dealt with: integrated circuit testing; fault diagnosis; integrated circuit design; logic testing; logic design; system-on-chip; design for testability; learning (artificial intelligence); field programmable gate arrays; IEEE standards.