Tri-level current-steering digital-to-analog converters (DACs) offer an appealing balance between resolution and static linearity, making them attractive to be employed as feedback DAC in high-resolution continuous-time Delta-Sigma-Modulator (CTDSM). However, they are susceptible to non-linearity caused by dynamic, signal-dependent switching errors degrading the overall performance. While such errors have been thoroughly analyzed in literature for single-bit current-steering DACs, they have not been thoroughly investigated for tri-level current-steering DACs. As a result, this paper investigates the sources of these errors and demonstrates their severity by analysis and simulations employing a tri-level DAC in an exemplary CTDSM. In addition, techniques for mitigating dynamic errors, including device sizing and switching schemes, are discussed to help mitigate the non-linearity.

As AI and its applications evolve, efficient hardware is required to run the novel algorithms. Compute platforms with a high degree of parallelism, such as matrix-vector multipliers, meet the need to process large homogeneous loads of operations. However, most of the matrix-vector multiplications required by the AI algorithms are larger than what the actual hardware supports. The operations must therefore be tiled into blocks that fit on the given hardware. Finally, the partial sums generated by the hardware for each tile must be accumulated or concatenated into the complete result. Especially with mixed-signal compute-in-memory architectures, this can lead to quantization on two levels. First, an ADC quantizes the partial sums generated for each tile. Then, the algorithm performs another quantization of the final result to limit bitwidth and resource consumption in adjacent computations. While quantizing only the partial sums or only the final results has been studied extensively, the combination of the two has yet to be investigated. This work introduces a simulator to understand the effects of quantization caused by multiple quantization steps on different levels. It is based on a generic, stochastic representation of value probabilities using histograms. Common operations such as scaling, rounding, and accumulation are implemented in this representation, allowing the effect of quantization to be studied in a matrix-vector-multiplier application. It is shown, that the selection of tilesize, ADC bitwidth and clipping technique form a complex trade-off, which can be solved using PSumSim. PSumSim is available under https://github.com/Joschua-Conrad/PSumSim.

Multibit (MB) quantization allows high resolution Delta-Sigma modulators (DSMs) with low oversampling ratio (OSR). Furthermore, it allows higher maximum stable amplitude (MSA), achieves reduced jitter sensitivity, and relaxes the dynamic requirements on the DSM loop-filter (LF). However, MB quantization adds a dominant source of non-linearity due to element mismatch in the MB digital-to-analog converter (DAC) which often dominates the performance. State of the art (SoA) presents many calibration techniques, though digital power and area consumption can be high and calibration time be significant. In this paper we target a calibration-free DAC based on dual quantization and propose to employ a Multistage noise SHaping (MASH) Digital-DSM (DDSM) to avoid architectural compromises between the main DSM LF and the DDSM DAC. The implementation trade-offs are illustrated, and stability constraints in both the main LF and the DDSM are addressed. An exemplary implementation is derived and simulated, and the results shall lay the foundation for future circuit implementations of MASH DDSM to realize MB DSM with intrinsically high linearity.

Active RC-Integrators are one of the main building blocks of continuous-time Delta-Sigma-Modulators (CTDSMs). The DC gain and gain-bandwidth product (GBW) of their Operational Ampifiers (OAs) play an important role in the modulator stability and performance in terms of signal-to-quantization-noise ratio (SQNR) as well as spurious-free dynamic range (SFDR). Negative-R assisted integrators have been introduced to reduce the CTDSMs sensitivity to OA non-idealities, where the negative-R has shown linearity improvements in low-power CTDSMs for relatively narrow bandwidth applications. However, the negative-R concept has not been widely applied for wideband applications. Wide-band CTDSMs in particular are more sensitive to the non-idealities of the OA GBW and especially in the associated phase-shift compared to their narrow-band counterparts. This paper provides insight into the effect of negative-R assistance on the GBW of the OA, where it is shown, that the phase-shift of the integrator due to finite GBW is not reduced by the negative-R assistance, and still remains an issue to be considered in the design of a wide-band CTDSMs.

This work presents a 600MS/s 10-bit single-channel asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) using a highly linear unit via-based delta-length capacitive digital-to-analog converter (C-DAC). The plain and regular segmented C-DAC structure is presented in detail, which provides close to 13-bit static matching with an area of only 1160 μm2. A Flash ADC is employed to pre-load some MSBs for improved conversion speed while also efficiently utilizing DAC segmentation, which is practically necessary in delta-length-based C-DACs. This ADC architecture can easily be extended to a time-interleaved SAR to fully take advantage of the fast Flash conversion. The ADC was fabricated in a 22nm FDSOI technology and achieves a SNDR of 51.37dB at 600MS/s with near Nyquist input while consuming 3.04mW from a 0.85V supply, which leads to a Walden FoM of 16.74fJ/conversion-step.

The performance of Continuous Time Delta-Sigma Modulators (CT-AEMs) is limited by clock jitter in the outermost feedback DAC. As one solution, FIR-DACs have been introduced to improve the modulators jitter robustness. In literature, those FIR-DACs have been described with equal coefficients for all taps. This paper investigates the effect of using non-equal symmetric taps on the modulators performance. A comparison between the two FIR filters (equal and non-equal symmetric taps) regarding jitter immunity, sensitivity to coefficient mismatch, complexity of the filters and the required compensation filter are presented. Furthermore, the effect of the FIR filters on the modulators dynamic requirements and its STF are discussed. The paper shows that symmetric non-equal coefficients outperform the equal coefficients configuration in all aspects without sacrificing hardware complexity, resulting in an extension of the modulator's jitter immunity limit and reduction of power consumption.

This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma- Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.

Intersymbol interference (ISI) plays an important role in the performance of continuous time delta-sigma modulators(CT-ΔΣM). Different techniques, such as return-to-zero DAC, ISI-shaping or calibration, were proposed in literature to tackle ISI in CT-ΔΣM. This paper investigates the effect of ISI in the outermost feedback digital-to-analog converter (DAC) for three different DAC structures; a single-bit DAC (SB), a multi-bit DAC (MB) and a FIR DAC. For each case, Monte-Carlo simulations were performed plotting the SFDR and SNDR for different rise/fall time mismatch percentages. The paper shows that DAC element mismatch due to rise and fall time variations in MB-DACs is more severe than ISI. However, for FIR-DAC the contrary is observed, the degradation in the performance due to ISI in FIR-DAC can be as severe as in SB-DACs when all FIR-taps are matched with regards to rise/fall time.

Recent state-of-the-art designs have shown that high jitter robustness and low integrator dynamics, thus better linearity can be achieved in a single-bit continuous-time (CT) delta-sigma (ΔΣ) modulator by adapting a finite impulse response (FIR) filter in the feedback digital-to-analog converter (DAC). However, when applying this to CT incremental ΔΣ modulators, after each periodic reset of the loop-filter, the output of each FIR tap is unrelated to the input signal and a certain amount of time is needed to settle back to a normal operation. This results in a severe swing overshoots at the output of the integrators in the initial phase of every incremental ΔΣ conversion cycle, which limits the dynamic range (DR) of the modulator and thus counteracts the benefits of the FIR DAC. This paper describes the challenges that come with acquiring an FIR DAC in an incremental ΔΣ modulator. Additionally, two design techniques are shown to mitigate the swing overshoots and achieve a normal operation of the modulator. This allows higher number of FIR taps to be used in an incremental ΔΣ modulator, which is very beneficial to promote high speed/resolution designs.

Dual quantization is an effective method to combine the benefit of single bit quantization, which results in inherently linearized DAC, and multibit quantization, which results in lower sampling rate. However, extra noise inserted in the loop due to requantization needs to be shaped out of the signal band to ensure the inband characteristics to remain as without the dual quantization. However, this additional shaping may result in extra noise injected into out of the band, which, if not filtered properly, may affect the loop dynamics and stability. Prior arts have used FIR filtering to filter out this additional digital quantization noise but in an ineffective way. In this paper, we show that the cutoff of the FIR filter can be reduced to much lower than Nyquist bandwidth(fs/2) and can be brought close to the signal bandwidth of the modulator resulting in a further improved performance.