Chiplet systems that stack heterogeneous dies via 2.5D/3D integration use JTAG-based test access ports (TAPs) to validate inter-die links and enable in-field diagnosis. However, these TAPs create a shared attack surface: penetrating a single die can potentially expose control of the entire stack. Current countermeasures involve embedding a complete cryptographic engine in each chiplet, which increases the area and locks the protocol at tape-out, leaving it susceptible to future unknown attacks. This paper proposes a Software-Defined Secure Island (SDSI) architecture that decouples security policies from hardwired logic while satisfying non-functional requirements. Each chiplet instantiates an ultra-lightweight Secure Island Controller (SIC) macro that performs only two XORs and two additions per handshake. Meanwhile, a centralized secure island runs heavyweight cryptography in firmware using the multi-round SASL-JTAG+ protocol. SDSI enables scalable, adaptable test access protection by decoupling security from hardware. An FPGA implementation shows that the SIC macro occupies 11% of the area of an AES- 128 core and 37% of a SHA256 core, yet it supports 256 - to 512-bit keys with negligible growth. A security analysis demonstrates immunity to replay attacks because the authentication data is refreshed with each session. All future upgrades, such as longer keys, stronger hashes, and additional rounds, are delivered via firmware, providing scalable, field-upgradable protection for heterogeneous chiplet systems.

Although advanced 3D chiplet packaging helps extend Moore’s-Law gains through vertical stacking of heterogeneous dies, it simultaneously introduces unprecedented thermal challenges. Shrinking 3D interconnects and rising current densities trap heat at through-silicon vias (TSVs) and micro-bumps, causing steep temperature gradients and thermo-mechanical stress that directly trigger early failures. Existing methods interact with finite-element analysis (FEA) tools mainly through manual, experience-based parameter tuning, inevitably making hot-spot detection time-consuming and error-prone. This paper establishes a text-interactive, thermal-failure-aware design framework for 3D chiplets that couples large language model (LLM)-accelerated thermal analysis with FEA simulation. A Python-driven Automatic Code Generation Model (ACGM) is invoked to automate geometry drawing, meshing, and boundary-condition assignment, enabling rapid analysis and prediction of hot-spot locations within densely stacked chiplets and TSVs. The proposed ACGM eliminates domain-expert dependence by abstracting cumbersome FEA parameter setting into natural-language commands, thereby lowering the entry barrier and cutting operation time. Deployment of the proposed ACGM streamlines intricate FEA operations and Python scripting into concise natural-language commands, enabling accurate layout-parameter tuning and shortened design cy-cles-establishing an AI-centric design-verification paradigm for advanced 3D chiplets.

As the CMOS technology continues to shrink, latches are becoming increasingly susceptible to multiple-node-upset caused by charge sharing in radiation environments. In this article, a low-cost quadruple-node-upset (QNU) self-recoverable latch based on cross-interlocking (Quad-CIRC) is proposed. By utilizing four cross-interlocking self-recoverable cells (CIRCs) for interlocking, complete QNU self-recovery is achieved with reduced sensitive nodes. Meanwhile, the majority of currently available QNU self-recoverable latches are primarily composed of C-elements-based redundancy, resulting in a significant increase in area overhead. However, Quad-CIRC effectively reduces area overhead while ensuring hardened capability through cross-interlocking of CIRCs. HSPICE-based simulations in 22 nm CMOS technology demonstrate that Quad-CIRC achieves a reduction of 69.08% on average of power consumption, an increase of 16.83% on average of delay, a reduction of 63.51% on average of power-delay-product (PDP), a reduction of 51.01% on average of area, a reduction of 83.44% on average of area-PDP (APDP), and an increase of 60.49% on average of critical charge, compared to five other QNU self-recoverable latches (QRHIL, MURLAV, LDAVPM,$QR-R_{11}-C_{2}$, and low-delay QNU self-recoverable).

Adaptive testing is a promising approach that practically ensures cost reduction and reliability for test strategy. In adaptive testing, the test content or pass/fail limits are not fixed as in conventional test, but depend on other test results of the currently or historically tested data. Based on recent progress in machine learning, a new Long Short-Term Memory (LSTM) which is more advanced than simple Recurrent Neuron Network (RNN) is proposed for defect screening. The simulation results have been compared with the other deep learning and traditional methods when patterns are increased and decreased. The comparisons show that the proposed RNN-based LSTM method has achieved remarkable improvements, i.e. 4.3% accuracy improvement and 2.32s time reduction during the test process.