With the development of sixth-generation (6G) wire-less communication networks, the security challenges are becoming increasingly prominent, especially for mobile users (MUs). As a promising solution, physical layer security (PLS) technology leverages the inherent characteristics of wireless channels to provide security assurance. Particularly, stacked intelligent metasurface (SIM) directly manipulates electromagnetic waves through their multilayer structures, offering significant potential for enhancing PLS performance in an energy efficient manner. Thus, in this work, we investigate an SIM-assisted secure communication system for MUs under the threat of an eavesdropper, addressing practical challenges such as channel uncertainty in mobile environments, multiple MU interference, and residual hardware impairments. Consequently, we formulate a joint power and phase shift optimization problem (JPPSOP), aiming at maximizing the achievable secrecy rate (ASR) of all MUs. Given the non-convexity and dynamic nature of this optimization problem, we propose an enhanced proximal policy optimization algorithm with a bidirectional long short-term memory mechanism, an offpolicy data utilization mechanism, and a policy feedback mechanism (PPO-BOP). Through these mechanisms, the proposed algorithm can effectively capture short-term channel fading and long-term MU mobility, improve sample utilization efficiency, and enhance exploration capabilities. Extensive simulation results demonstrate that PPO-BOP significantly outperforms benchmark strategies and other deep reinforcement learning algorithms in terms of ASR.

The independence of logic optimization and technology mapping poses a significant challenge in achieving high-quality synthesis results. Recent studies have improved optimization outcomes through collaborative optimization of multiple logic representations and have improved structural bias through structural choices. However, these methods still rely on technology-independent optimization and fail to truly resolve structural bias issues. This paper proposes a scalable and efficient framework based on Mixed Structural Choices (MCH). This is a novel heterogeneous mapping method that combines multiple logic representations with technology-aware optimization. MCH flexibly integrates different logic representations and stores candidates for various optimization strategies. By comprehensively evaluating the technology costs of these candidates, it enhances technology mapping and addresses structural bias issues in logic synthesis. Notably, the MCH-based lookup table (LUT) mapping algorithm set new records in the EPFL Best Results Challenge by combining the structural strengths of both And-Inverter Graph (AIG) and XOR-Majority Graph (XMG) logic representations. Additionally, MCH-based ASIC technology mapping achieves a $3.73 \%$ area and $8.94 \%$ delay reduction (balanced), 20.35% delay reduction (delay-oriented), and $\mathbf{2 1. 0 2 \%}$ area reduction (area-oriented), outperforming traditional structural choice methods. Furthermore, MCH-based logic optimization utilizes diverse structures to surpass local optima and achieve better results.

Mapping to$k$-input lookup tables ($k$-LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the dependency of mapping results on the inherent graph structure, often leading to suboptimal results. To address this, we present ELMap, an area-driven LUT mapping framework. It incorporates structural choice during the collapsing phase. This enables dynamic decomposition, maximizing local-to-global optimization transfer. To ensure seamless integration between the optimization and mapping processes, ELMap leverages exact$k$-LUT synthesis to generate area-optimal sub-LUT networks. Experiments on the EPFL benchmark suite demonstrate that ELMap significantly outperforms state-of-the-art methods. Specifically, in 6-LUT mapping, ELMap reduces the average LUT area by 8.5% and improves the area-depth-product (ADP) by 5.8%. In 4-LUT remapping, it reduces the average LUT area by 17.6% and improves the ADP by 2.4%.

Stacked intelligent metasurfaces (SIMs) have emerged as a promising technology for realizing wave-domain signal processing, while the fixed SIMs will limit the communication performance of the system compared to the mobile SIMs. In this work, we consider a UAV-mounted SIMs (UAV-SIMs) assisted communication system, where UAVs as base stations (BSs) can cache the data processed by SIMs, and also as mobile vehicles flexibly deploy SIMs to enhance the communication performance. To this end, we formulate a UAV-SIM-based joint optimization problem (USBJOP) to comprehensively consider the association between UAV-SIMs and users, the locations of UAV-SIMs, and the phase shifts of UAV-SIMs, aiming to maximize the network capacity. Due to the non-convexity and NP-hardness of USBJOP, we decompose it into three sub-optimization problems, which are the association between UAV-SIMs and users optimization problem (AUUOP), the UAV location optimization problem (ULOP), and the UAV-SIM phase shifts optimization problem (USPSOP). Then, these three sub-optimization problems are solved by an alternating optimization (AO) strategy. Specifically, AUUOP and ULOP are transformed to a convex form and then solved by the CVX tool, while we employ a layer-by-layer iterative optimization method for USPSOP. Simulation results verify the effectiveness of the proposed strategy under different simulation setups.

We introduce DeepCell, a novel circuit representation learning framework that effectively integrates multiview information from both And-Inverter Graphs (AIGs) and Post-Mapping (PM) netlists. At its core, DeepCell employs a self-supervised Mask Circuit Modeling (MCM) strategy, inspired by masked language modeling, to fuse complementary circuit representations from different design stages into unified and rich embeddings. To our knowledge, DeepCell is the first framework explicitly designed for PM netlist representation learning, setting new benchmarks in both predictive accuracy and reconstruction quality. We demonstrate the practical efficacy of DeepCell by applying it to critical EDA tasks such as functional Engineering Change Orders (ECO) and technology mapping. Extensive experimental results show that DeepCell significantly surpasses state-of-the-art open-source EDA tools in efficiency and performance. The code is available at https://github.com/cure-lab/DeepCell.

The Internet of Things (IoT) is widely applied for forest monitoring, since the sensor nodes (SNs) in IoT network are low cost and have computing ability to process the monitoring data. To further improve the performance of forest monitoring, uncrewed aerial vehicles (UAVs) are employed as the data processors to enhance computing capability. However, efficient forest monitoring with limited energy budget and computing resource presents a significant challenge. For this purpose, this article formulates a multiobjective optimization framework to simultaneously consider three optimization objectives, which are minimizing the maximum computing delay, minimizing the total motion energy consumption, and minimizing the maximum computing resource, corresponding to efficient forest monitoring, energy consumption reduction, and computing resource control, respectively. Due to the hybrid solution space that consists of continuous and discrete solutions, we propose a diffusion-model-enhanced improved multiobjective grey wolf optimizer (IMOGWO) to solve the formulated framework. The simulation results show that the proposed IMOGWO outperforms other benchmarks for solving the formulated framework. Specifically, for a small-scale network with 6 UAVs and 50 SNs, compared to the suboptimal benchmark, IMOGWO reduces the motion energy consumption and the computing resource by 53.32% and 9.83%, respectively, while maintaining computing delay at the same level. Similarly, for a large-scale network with 8 UAVs and 100 SNs, IMOGWO achieves reductions of 41.81% in motion energy consumption and 7.93% in computing resource, with the computing delay also remaining comparable.

Devices within the marine Internet of Things (MIoT) can connect to low Earth orbit (LEO) satellites and unmanned aerial vehicles (UAVs) to facilitate low-latency data transmission and execution, as well as enhanced-capacity data storage. However, without proper traffic handling strategy, it is still difficult to effectively meet the low-latency requirements. In this paper, we consider a cooperative satellite-aerial-MIoT network (CSAMN) for maritime edge computing and maritime data storage to prioritize delay-sensitive (DS) tasks by employing mobile edge computing, while handling delay-tolerant (DT) tasks via the store-carry-forward method. Considering the delay constraints of DS tasks, we formulate a constrained joint optimization problem of maximizing satellite-collected data volume while minimizing system energy consumption by controlling four interdependent variables, including the transmit power of UAVs for DS tasks, the start time of DT tasks, computing resource allocation, and offloading ratio. To solve this non-convex and non-linear problem, we propose a joint computation offloading and resource management (JCORM) algorithm using the Dinkelbach method and linear programming. Our results show that the volume of data collected by the proposed JCORM algorithm can be increased by up to 41.5% compared to baselines. Moreover, JCORM algorithm achieves a dramatic reduction in computational time, from a maximum of 318.21 seconds down to just 0.16 seconds per experiment, making it highly suitable for real-time maritime applications.

Traditional logic synthesis methods are based on Boolean logic, which tends to produce redundant logic structures in dense circuit applications, such as complex number operations and error detection/correction coding. Traditional Boolean and Reed-Muller (TB-RM) logic synthesis method combining traditional Boolean (TB) logic and Reed-Muller (RM) logic can improve comprehensive optimization indexes and reduce cost. The existing TB design method is not effective when dealing with constrained systems with high-resource utilization requirements. In addition, traditional synthesis methods do not consider multiobjective optimization of area, power consumption and reliability. To solve these problems, we propose an effective dual logic synthesis method (EDSM), which includes dual logic detection method (DDM) and differential evolution algorithm based on multidimensional mutation strategy (DE-MMS). DDM can complete the logic detection function, and DE-MMS can further optimize the polarity. In addition, to evaluate the soft errors occurring more efficiently at the logic level, we propose a soft error rate (SER) estimation model. Experimental results show that compared with state-of-the-art evolutionary algorithms, EDSM can search for optimal solutions in all optimization problems; compared with commonly used TB-based minimization methods, EDSM has obvious advantages in multiobjective optimization of area, power consumption and SER. After 6-LUT FPGA technology and standard cells mapping, by selecting area as the optimal cost implementation, we obtain average improvements in the area of 14% and 2%, respectively.

Cooperative reconfigurable intelligent surfaces (RISs) are promising technologies for 6 G networks to support a great number of users. Compared with the fixed RISs, the properly deployed RISs may improve the communication performance with less communication energy consumption, thereby improving the energy efficiency. In this paper, we consider a cooperative unmanned aerial vehicle-mounted RISs (UAV-RISs)-assisted cellular network, where multiple RISs are carried and enhanced by UAVs to serve multiple ground users (GUs) simultaneously such that achieving the three-dimensional (3D) mobility and opportunistic deployment. Specifically, we formulate an energy-efficient communication problem based on multi-objective optimization framework (EEComm-MOF) to jointly consider the beamforming vector of base station (BS), the location deployment and the discrete phase shifts of UAV-RIS system so as to simultaneously maximize the minimum available rate over all GUs, maximize the total available rate of all GUs, and minimize the total energy consumption of the system, while the transmit power constraint of BS is considered. To comprehensively solve EEComm-MOF which is an NP-hard and non-convex problem with constraints, a non-dominated sorting genetic algorithm-II with a continuous solution processing mechanism, a discrete solution processing mechanism, and a complex solution processing mechanism (INSGA-II-CDC) is proposed. Simulations results demonstrate that the proposed INSGA-II-CDC can solve EEComm-MOF effectively and outperforms other benchmarks under different parameter settings. Moreover, the stability of INSGA-II-CDC and the effectiveness of the improved mechanisms are verified. Finally, the implementability analysis of the algorithm is given.

Unmanned aerial vehicle (UAV)-assisted mobile edge computing (MEC) is emerging as a promising paradigm to provide aerial-terrestrial computing services in close proximity to mobile devices (MDs). However, meeting the demands of computation-intensive and delay-sensitive tasks for MDs poses several challenges, including the demand-supply contradiction between MDs and MEC servers, the demand-supply discrepancy between MDs and MEC servers, the trajectory control requirements on energy efficiency and timeliness, and the different time-scale dynamics of the network. To address these issues, we first present a hierarchical architecture by incorporating terrestrial-aerial computing capabilities and leveraging UAV flexibility. Furthermore, we formulate a joint computing resource allocation, computation offloading, and trajectory control problem to maximize the system utility. Since the problem is a non-convex and NP-hard mixed integer nonlinear programming (MINLP), we propose a two-timescale joint computing resource allocation, computation offloading, and trajectory control (TJCCT) approach for solving the problem. In the short timescale, we propose a price-incentive model for on-demand computing resource allocation and a matching mechanism-based method for computation offloading. In the long timescale, we propose a convex optimization-based method for UAV trajectory control. Besides, we theoretically prove the stability and polynomial complexity of TJCCT. Extensive simulation results demonstrate that the proposed TJCCT is able to achieve superior performances in terms of the system utility, average processing rate, average completion delay, average completion ratio, and average cost, while meeting the energy constraints despite the trade-off of the increased energy consumption.

Logic synthesis is crucial in digital design automation, significantly enhancing performance, reducing area, and lowering power consumption through technology-independent optimization followed by technology mapping. Logic rewriting, a key strategy for optimization, iteratively replaces portions of logic circuits with more compact implementations. Despite historical advancements, challenges remain in subgraph selection, technology-dependent metrics, and performance-runtime trade-offs. This article presents a novel Te chnology- a ware logic R e W riting ( TeaRW ) framework to address these challenges. TeaRW incorporates a technology-aware rewriting algorithm that evaluates post-mapping netlist metrics during the technology-independent optimization phase. It employs four distinct subgraph rewriting techniques to maximize the effectiveness of local optimization. For efficiency, TeaRW utilizes an optimized logic representation database derived from exact synthesis, enabling cost-effective replacements. Experimental results on real-world benchmarks show improvements over the ABC tool, including an average Area-Delay-Product (ADP) improvement of 8.18% in delay-oriented optimization and 0.28% in area-oriented optimization when compared to state-of-the-art optimization scripts.

This paper introduces a novel circuit simulator of k-input lookup table (k-LUT) networks, based on semi-tensor product (STP). STP-based simulators use computation of logic matrices, the primitives of logic networks, as opposed to relying on bitwise logic operations for simulation of k- LUT networks. Experimental results show that our STP-based simulator reduces the runtime by an average of 7.2 ×. Furthermore, we integrate this proposed simulator into a SAT sweeper. Through a combination of structural hashing, simulation, and SAT queries, SAT sweeper simplifies logic networks by systematically merging graph vertices from input to output. To enhance the efficiency, we used STP-based exhaustive simulation, which significantly reduces the number of false equivalence class candidates, thereby improving the computational efficiency by reducing the number of SAT calls required. When compared to the state-of-the-art SAT sweeper, our method demonstrates an average 35% runtime reduction.

Emerging 6G technologies, such as terahertz communication and ultra-massive multiple-input multiple-output, offer exciting prospects but face challenges like limited range and multipath interference. In this paper, we seek to use an unmanned aerial vehicle (UAV)-carried intelligent reflecting surface (IRS) to assist the terrestrial mmWave networks. Specifically, we consider a typical urban scenario where a UAV-carried IRS rebuilds the line of sight (LoS) channel between a mobile user and a base station under the existence of obstacles. Then, we formulate an optimization problem to maximize the transmission rates and minimize the UAV energy consumption, by jointly optimizing the UAV trajectory and the phase shifts of IRS. The problem is non-convex and with high dynamic, and thus we propose a deep reinforcement learning (DRL)-based algorithm with neural episodic control, long short-term memory (LSTM), and a phase control method to solve the problem, thereby enhancing the stability and accelerate convergence speed. Simulation results demonstrate that the proposed algorithm effectively addresses the problem and outperforms other benchmark algorithms.

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption.

Abstract Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an “AI4EDA” approach falls short of achieving a holistic design synthesis and understanding, overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This study argues for a paradigm shift from AI4EDA towards AI-rooted EDA from the ground up, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, register-transfer level (RTL) designs, circuit netlists, and physical layouts. We champion the creation of large circuit models (LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-rooted philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound “shift-left” in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design-tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area (PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems’ capabilities.

Boolean satisfiability (SAT)-based exact synthesis has made significant progress in recent years, particularly in logic rewriting for the identification of potential subnetwork replacements. However, existing rewriting algorithms suffer from two major drawbacks: 1) inflexibility due to precomputed potential replacement candidates and 2) high-computational complexity of off-the-shelf conjunction normal form (CNF)-based SAT solvers. In this article, we propose a novel semi-tensor product (STP)-based exact synthesis approach for logic rewriting. The STP-based exact synthesis encodes Boolean functions into logic matrices and uses circuit-based all solutions SAT (AllSAT) solver to obtain all optimal replacement candidates with a single pass. Additionally, we improve the subnetwork selection strategy to allow flexible rewriting by selecting the most cost-effective implementation of all optimal candidates. Experimental results, compared with the state-of-the-art logic synthesis tool ABC, show that proposed STP-based exact synthesis reduces 41% runtime on average and solves all instances within a time limit. Moreover, after mapping into 6-LUT FPGA technology and standard cells, we obtain average improvements in the area of 6% and 18%, respectively.

Unmanned aerial vehicles (UAVs)-aided device-to-device (D2D) networks have attracted great interests with the development of 5G/6G communications, while there are several challenges about resource scheduling in UAVs-aided D2D networks. In this work, we formulate a UAVs-aided D2D network resource scheduling optimization problem (NetResSOP) to comprehensively consider the number of deployed UAVs, UAV positions, UAV transmission powers, UAV flight velocities, communication channels, and UAV-device pair assignment so as to maximize the D2D network capacity, minimize the number of deployed UAVs, and minimize the average energy consumption over all UAVs simultaneously. The formulated NetResSOP is a mixed-integer programming problem (MIPP) and an NP-hard problem, which means that it is difficult to be solved in polynomial time. Moreover, there are trade-offs between the optimization objectives, and hence it is also difficult to find an optimal solution that can simultaneously make all objectives be optimal. Thus, we propose a non-dominated sorting genetic algorithm-III with a Flexible solution dimension mechanism, a Discrete part generation mechanism, and a UAV number adjustment mechanism (NSGA-III-FDU) for solving the problem comprehensively. Simulation results demonstrate the effectiveness and the stability of the proposed NSGA-III-FDU under different scales and settings of the D2D networks.

In logic synthesis, Boolean satisfiability (SAT) is widely used as a reasoning engine, especially for exact synthesis. By representing input formulas as logic circuits instead of conjunction normal forms (CNFs) as in off-the-shelf CNF-based SAT solvers, circuit-based SAT solvers enable decoding after solution to be easier. An exact synthesis method based on a semi-tensor product (STP) circuit solver is presented in this paper. As opposed to other SAT-based exact synthesis algorithms, synthesized Boolean functions are encoded into STP canonical forms and can be solved by STP-based circuit SAT solver in our method. It can also obtain all optimal solutions in one pass. In particular, all solutions are expressed as 2-lookup tables (LUTs), rather than homogeneous logic representations. Hence, different costs can be considered when selecting the optimal circuit. In experiments, we demonstrate that our method accelerates the runtime up to 225.6X while reducing timeout instances by up to 88%.

Circuit representation learning aims to obtain neural repre-sentations of circuit elements and has emerged as a promising research direction that can be applied to various EDA and logic reasoning tasks. Existing solutions, such as DeepGate, have the potential to embed both circuit structural information and functional behavior. However, their capabilities are limited due to weak supervision or flawed model design, resulting in unsatisfactory performance in downstream tasks. In this paper, we introduce Deep Gate2, a novel functionality-aware learning framework that significantly improves upon the original DeepGate solution in terms of both learning effectiveness and efficiency. Our approach involves using pairwise truth table differences between sampled logic gates as training supervision, along with a well-designed and scalable loss function that explicitly considers circuit functionality. Additionally, we consider inherent circuit characteristics and design an efficient one-round graph neural network (GNN), resulting in an order of magnitude faster learning speed than the original DeepGate solution. Experimental results demonstrate significant improvements in two practical downstream tasks: logic synthesis and Boolean satisfiability solving. The code is available at https://github.com/cure-lablDeepGate2.

Unmanned aerial vehicle (UAV)-enabled wireless powered communication networks (WPCNs) are promising technologies in 5G/6G wireless communications, while there are several challenges about UAV power allocation and scheduling to enhance the energy utilization efficiency, considering the existence of obstacles. In this work, we consider a UAV-enabled WPCN scenario that a UAV needs to cover the ground wireless devices (WDs). During the coverage process, the UAV needs to collect data from the WDs and charge them simultaneously. To this end, we formulate a joint-UAV power and three-dimensional (3D) trajectory optimization problem (JUPTTOP) to simultaneously increase the total number of the covered WDs, increase the time efficiency, and reduce the total flying distance of UAV so as to improve the energy utilization efficiency in the network. Due to the difficulties and complexities, we decompose it into two sub optimization problems, which are the UAV power allocation optimization problem (UPAOP) and UAV 3D trajectory optimization problem (UTTOP), respectively. Then, we propose an improved non-dominated sorting genetic algorithm-II with$K$-means initialization operator and Variable dimension mechanism (NSGA-II-KV) for solving the UPAOP. For UTTOP, we first introduce a pretreatment method, and then use an improved particle swarm optimization with Normal distribution initialization, Genetic mechanism, Differential mechanism and Pursuit operator (PSO-NGDP) to deal with this sub optimization problem. Simulation results verify the effectiveness of the proposed strategies under different scales and settings of the networks.

Unmanned aerial vehicle (UAV)-enabled wireless powered communication networks (WPCN) are promising technologies in Internet of Things (IoTs). However, energy-constrained devices and connectivity in complex environments are two major challenges for IoTs. We consider a UAV-enabled WPCN scenario that a UAV can connect with the ground IoT devices (IoTDs). To connect and fly faster, UAV needs to be scheduled reasonably and the corresponding trajectory should be optimized. Thus, we formulate a UAV scheduling and trajectory optimization problem (USTOP) to minimize the total time so that improving the charging and transmission efficiency. Since conventional methods are difficult to solve USTOP, we propose an improved simulated annealing (ISA) with the variable size changing mechanism, the conflict resolution mechanism and the hybrid evolution method to solve it. Simulation results verify the effectiveness and performance of ISA under different scales of the network, and the stability of the proposed algorithm is verified.

Unmanned aerial vehicle (UAV) communication is a promising technology in 5G/6G wireless communications. However, there are several challenges for ensuring secure communications in practical scenarios. In this paper, we consider a UAV-enabled communication scenario that a UAV needs to maintain secure communication with the ground communication nodes (GCNs), subject to the known ground eavesdropping nodes (GENs). UAV needs to select optimal communication positions and avoid obstacles. We formulate a UAV secrecy scheduling optimization problem (USSOP) to maximize the average secrecy rate and the minimum secrecy rate jointly. Then, we propose a particle swarm optimization with $\underline {normal}$ distribution initialization, $\underline {differential}$ mechanism and $\underline {avoiding}$ obstacles operator (PSONDA) to solve the USSOP. Simulation results show that this method performs better than other comparison algorithms.

Wireless rechargeable sensor networks with a charging unmanned aerial vehicle (CUAV) have broad application prospects in the power supply of the rechargeable sensor nodes (SNs). However, how to schedule a CUAV and design the trajectory to improve the charging efficiency of the entire system is still a vital problem. In this article, we formulate a joint-CUAV scheduling and trajectory optimization problem (JSTOP) to simultaneously minimize the hovering points of CUAV, the number of the repeatedly covered SNs, and the flying distance of CUAV for charging all SNs. Due to the complexity of JSTOP, it is decomposed into two optimization subproblems that are CUAV scheduling optimization problem (CSOP) and CUAV trajectory optimization problem (CTOP). CSOP is a hybrid optimization problem that consists of the continuous and discrete solution space, and the solution dimension in CSOP is not fixed since it should be changed with the number of hovering points of CUAV. Moreover, CTOP is a completely discrete optimization problem. Thus, we propose a particle swarm optimization (PSO) with a flexible dimension mechanism, a$K$-means operator, and a punishment-compensation mechanism (PSOFKP) and a PSO with a discretization factor, a 2-opt operator, and a path crossover reduction mechanism (PSOD2P) to solve the converted CSOP and CTOP, respectively. Simulation results evaluate the benefits of PSOFKP and PSOD2P under different scales and settings of the network, and the stability of the proposed algorithms is verified.

Wireless rechargeable sensor networks (WRSNs) with a charging UAV (CUAV) have the broad application prospects for the power supply of the rechargeable sensor nodes (SNs). However, how to schedule the CUAV so that improving the charging efficiency of the whole system is still a vital problem. In this paper, we formulate a scheduling optimization problem of CUAV (SOPCUAV) to jointly reduce the hovering number of the CUAV and the duplicate coverage of SNs for enhancing the charging performance. Then, we propose an improved particle swarm optimization (IPSO) algorithm with the flexible dimension mechanism, using K - means operator to find the hovering position of CUAV and punishment and compensation mechanism to solve the formulated SOPCUAV. Simulation results demonstrate the effectiveness and performance of the proposed algorithm.