Demo Data from VLDB 2026 / reviewers in the wild / expert
Harveen Kaur
dblp:245/6084
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 50% Hardware accelerators and domain-specific architectures · 50% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
in-memory computing |
0.4 | 1 | 2019 | NNPIM: A Processing In-Memory Architecture for Neural Network Acceleration · IEEE Trans. Computers 2019 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network acceleration |
0.4 | 1 | 2019 | NNPIM: A Processing In-Memory Architecture for Neural Network Acceleration · IEEE Trans. Computers 2019 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.4 | 1 | 2019 | NNPIM: A Processing In-Memory Architecture for Neural Network Acceleration · IEEE Trans. Computers 2019 |
Memory systems
processing-in-memory |
0.4 | 1 | 2019 | NNPIM: A Processing In-Memory Architecture for Neural Network Acceleration · IEEE Trans. Computers 2019 |
Methods — techniques the papers use, named apart from their topics
weight sharing · 0.4crossbar memory · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Technology, home health care, and heart failure: a qualitative analysis with multiple stakeholdersabstractHome health aides (HHAs) increasingly being used by adults with heart failure for long-term assistance and post-hospitalization care. Despite being heavily involved in numerous aspects of heart failure management, most HHAs have not received heart failure training. They also struggle to get in touch with supervising nurses or other members of the care team when they have clinical questions, which may result in unnecessary visits to the emergency room. In addition, despite serving as a backbone in the health system for patients, HHAs, who are mostly women and minorities, are a marginalized and vulnerable group of frontline caregivers, enduring erratic employment, low wages, discrimination, and high levels of burnout. Although digital technologies could help to address many of the challenges HHAs face, little is known about the current impact of technology on HHAs work practices. To this end, we conducted a multi-stakeholder qualitative study with 38 participants in New York City using semi-structured interviews and focus groups. We uncover the ways in which technology is used, the complex socio-technical factors that underpin heart failure care, and stakeholder suggestions for how technology could improve HHAs work. Building on these insights, we synthesize design opportunities for researchers and designers interested in developing tools that support the delivery of home health care for patients suffering from life-threatening diseases like heart failure. Fabian Okeke, Emily Tseng, Benedetta Piantella, Mikaela Brown, Harveen Kaur, Madeline R. Sterling, Nicola Dell |
COMPASS | 5 |
| 2019 | NNPIM: A Processing In-Memory Architecture for Neural Network AccelerationabstractNeural networks (NNs) have shown great ability to process emerging applications such as speech recognition, language recognition, image classification, video segmentation, and gaming. It is therefore important to make NNs efficient. Although attempts have been made to improve NNs' computation cost, the data movement between memory and processing cores is the main bottleneck for NNs' energy consumption and execution time. This makes the implementation of NNs significantly slower on traditional CPU/GPU cores. In this paper, we propose a novel processing in-memory architecture, called NNPIM, that significantly accelerates neural network's inference phase inside the memory. First, we design a crossbar memory architecture that supports fast addition, multiplication, and search operations inside the memory. Second, we introduce simple optimization techniques which significantly improves NNs' performance and reduces the overall energy consumption. We also map all NN functionalities using parallel in-memory components. To further improve the efficiency, our design supports weight sharing to reduce the number of computations in memory and consecutively speedup NNPIM computation. We compare the efficiency of our proposed NNPIM with GPU and the state-of-the-art PIM architectures. Our evaluation shows that our design can achieve 131.5× higher energy efficiency and is 48.2× faster as compared to NVIDIA GTX 1,080 GPU architecture. Compared to state-of-the-art neural network accelerators, NNPIM can achieve on an average 3.6× higher energy efficiency and is 4.6× faster, while providing the same classification accuracy. Saransh Gupta, Mohsen Imani, Harveen Kaur, Tajana Rosing |
IEEE Trans. Computers | 3 |