A modular architecture for very fast digital signal processing (DSP) elements are presented. The computation is performed over finite rings (or fields) and is able to emulate processing over the integer ring using residue number systems. The computations are restricted to closed operations (ring or field binary operators) with the ability to perform limited scaling operations. Computations naturally defined over finite mathematical systems are also easily implemented using this approach. The technique evolves from the decomposition of each closed calculation using the ring/field associativity property. Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. The pipeline cycle is determined from the generic cell and is predicted to be very fast by a critical path analysis. The cells are matched to the VLSI medium, and the resulting array structures are very dense. Examples of DSP applications are given to illustrate the technique, and example cell and array VLSI layouts are presented for a 3- mu m CMOS process.>

The Residue Number System (RNS), its concept, computational power, and applications have been investigated in the past [1,6,7]. Most of the studies have resulted in realizations suitable for discrete implementation [2,8]. This paper introduces a linear systolic array architecture for an RNS based FIR filter suitable for VLSI fabrication. The array, which is completely pipelined, consists of modular cells which only communicate to their nearest neighbor. The connected cells constitute a linear systolic array, and the construction of the cell is such that it can be programmed to function in many different DSP tasks. The final result is the construction of a linear systolic ROM that effectively replaces the previously used discrete ROM arrays.