Crosstalk noise has been strongly threatened the signal integrity of interconnects in new sub-micrometer technology nodes. The crosstalk prediction helps to avoid crosstalk consequences. Static crosstalk models cannot predict crosstalk faults intensified by thermal, fab-induced, and temporal uncertainties. The goal of the paper is to avoid crosstalk by the use of a dynamic crosstalk predictor which can adapt itself in the presence of uncertainties. To begin with, the neural network model of the crosstalk phenomenon would be extracted based on data transition of communication wires. This model is implemented as an on-chip crosstalk predictor. In addition, this predictor would be trained on-chip by hardware implementing the learning algorithm. Simulation results show that the proposed predictor is much more tolerant of uncertainties than the static predictors.

In very deep sub-micrometer technology nodes, signal integrity of interconnects has been drastically jeopardized by crosstalk noise. To make a communication link reliable against crosstalk faults, different detection, correction, and avoidance methods have been proposed at the cost of redundant spatial and information overheads. In this paper, we propose a crosstalk prediction hardware based on an abstract model deduced from low-level interconnect evaluation for new technologies. This predictor monitors the data pattern to be sent through a communication bus and predicts those likely subjected to the crosstalk fault. Thus, to prevent crosstalk faults, the predictor dynamically engages an avoidance or detection mechanism. Top-level buses are the target of the proposed method. Simulation results reveal that the proposed communication channel is more efficient in terms of crosstalk alleviation as well as area and performance overhead compared to the state of the art reliability methods.

At the system-level, cores are put together using interconnects that we refer to as high-level communication links. This paper presents an abstract interconnect model for cores connecting to each other to estimate, and thus model, crosstalk noise resulting from the physical properties of interconnects. Such models consider the effects of adjacent wires on each other in the form of weighted transitions. Transition weights are extracted by DC analysis of interconnect SPICE models. These weights form our raw-models, which are then specialized by AC analysis of RLC interconnect models in a mixed-signal simulation environment. The latter analyses establish weight thresholds for glitch faults. Our simulations show that if we were to use only DC-based models for crosstalk faults, we would be over / under-estimating faults as compared with models that are specialized by AC simulation runs. For higher data rates, Specialized models perform an order of magnitude better than DC-based models for crosstalk fault detection.

In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number of LUT transistors experience severe stress rates. Therefore, an algorithm is presented to select several alternative configurations for each LUT. Alternative configurations are obtained by LUT input reordering. These alternative configurations are rotationally loaded into the FPGA. Experimental results shows that our method achieves 263 and 14.1 percent Mean Time To Failure (MTTF) improvement for Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI), respectively. Additionally, due to changing only local routings, our method imposes up to 1 percent performance overhead to the systems.

As digital design moves into higher abstraction levels, chip-level communications become more complex, thus harder to consider low-level interconnection signal effects. Abstract interconnect models are required in order to be able to bring signal integrity issues such as crosstalk into the hands of the high-level system designer. Such abstraction can be based on, and back-annotated from, the existing crosstalk fault models, of which MDSI is a candidate. While MDSI, by considering RLC interconnect effects and not just RC, is an improvement over some other proposed models, its simplified adjacent line effects makes it inadequate for the newer technologies. For the purpose of back-annotating physical properties for system-level crosstalk modeling, we have developed a new model based on MDSI that we refer to as Weighted-MDSI. In this modeling, the effect of lines causing a cross-talk noise on a victim line is weighted by their distances to the victim. This paper extracts parameters of our presented Weighted-MDSI from HSPICE simulation runs. The parameters extracted as such are programmed into SystemC communication channels for high-level reliability evaluations and other system-level decision makings. Furthermore, SystemC-AMS models are considered as an alternative for adjusting Weighted-MDSI parameters, and for verification purposes.