This paper presents a method for accurately accounting for Local Layout Effect (LLE) in Static Timing Analysis (STA). Conventional timing analysis methodologies often add timing margins at the block level to account for LLE, despite its predictable nature, due to the challenges of integrating local effects into conventional STA flow. The proposed method addresses this challenge by incorporating detailed layout information into the timing analysis, which accurately models LLE. The resulting approach reduces timing margins, improving the performance of designs while maintaining accuracy. The proposed methodology extracts physical layout parameters and converts them to threshold voltage and mobility shift, which are then used to adjust the timing of the circuit. This adjustment is made by referring to a characterized delay sensitivity table. Compared to traditional methodologies that use timing margins, the proposed methodology significantly reduces pessimism, allowing for more optimization opportunities. The cost of this approach is only a small increase in the characterization cost, making it a cost-effective solution. The proposed methodology has been successfully applied in practice to analyze and optimize designs under timing effects induced near RX width transitions. The results showed an improvement of around 2.6% in the maximum frequency and a 6% reduction in leakage power. This highlights the effectiveness of the proposed approach in achieving better design optimization while maintaining accurate timing analysis.

Layout-dependent effect causes variation in device performance as well as mismatch in model-hardware correlation in sub-10 nm nodes. In order to effectively explore the power-performance envelope for IC design, cell libraries must provide cells with different diffusion heights, leading to neighbor diffusion effect (NDE) due to inter-cell diffusion height change (diffusion steps). Special filler cells can protect against steps to functional cells, but with nontrivial area overhead. In this paper, we develop dynamic programming (DP)-based single-row and multi-row (MR) detailed placement optimizations that optimally reduce inter-cell diffusion steps to mitigate the impacts of NDE. Compared to previous works, our algorithms are capable of exploring richer solution spaces as they support cell flipping, relocating, and reordering across cell rows; we also consider cell displacement, flipping, and wirelength costs. Notably, to our knowledge, our MR DP-based optimization algorithm is the first to optimally handle inter-row cell relocating and reordering. We also explore various metaheuristic configurations to further improve the solution quality. Last, we develop a timing-aware approach, which is capable of creating intentional steps that can potentially improve the drive strength of critical cells. The optimality is in terms of maximum diffusion step reduction, for given displacement range, reordering range and cell variants. Additionally, the above range definitions, including the definition of the ordering of cells, depend on assumptions described in Sections IV and V.

In sub-10nm, nodes, a change or step in diffusion height between adjacent standard cells causes yield loss as well as a form of model-hardware miscorrelation called neighbor diffusion effect (NDE). Cell libraries must inevitably have multiple diffusion heights (numbers of fins in PFETs and NFETs) in order to enable flexible exploration of the power-performance envelope for design. However, this brings step-induced risks of NDE, for which guardbanding is costly, as well as yield loss. Special filler cells can protect against harmful NDE effects, but are costly in terms of area. In this work, we develop dynamic programming-based single-row and double-row detailed placement optimizations that optimally minimize the impacts of NDE. Our algorithms support a richer set of cell movements than in previous works - i.e., flipping, relocating and reordering within the original row; we also consider cell displacement and flipping costs. Importantly, to our knowledge, our dynamic programming-based optimal detailed placement algorithm is the first to handle multiple rows with multiple-height cells that can be reordered. We further develop a timing-aware approach, which is capable of recovering (or, improving) the worst negative slack (WNS) by creating additional diffusion steps around timing-critical cells.