This paper presents a low-noise class-F23voltage-controlled oscillator (VCO) with harmonic resonance expansion and$2^{\mathrm {nd}}$/$3^{\mathrm {rd}}$-harmonic outputs for multiband mm-wave applications. By using a single four-coil transformer to extend the common-mode (CM) and differential-mode (DM) harmonic resonance bandwidths, the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic resonances can be acquired without additional frequency alignment calibration. Meanwhile, benefiting from the favorable differential response at the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic frequencies, the corresponding harmonic frequency outputs are extracted, simultaneously. Fabricated in 65-nm CMOS process, the proposed VCO achieves a frequency tuning range (FTR) of 20.8% from 10.71 GHz to 13.20GHz with 1-MHz offset phase noise (PN) from -117.4 to -114.5 dBc/Hz, while consuming 7.8-9.8 mW at 0.6 V. The VCO core area is only 0.054 mm2and the flicker noise corner is 310-450 kHz. The figure-of-merit (FoM) at 10-MHz offset scores 189.8-191.7 dBc/Hz. The harmonic outputs achieve a FTR of 21.42-26.40 GHz and 32.13-39.60 GHz, with a 1-MHz-offset PN from –110.5 to –107.5 dBc/Hz and –107.6 to –104.8 dBc/Hz.

This brief proposes a 7.4–9.2-GHz low-noise fractional-N differential sampling phase-locked loop (DSPLL), which features doubled phase detector (PD) gain. By using the phase-domain and voltage-domain hybrid calibration, the accumulated quantization error (Q-error) of the delta-sigma modulator (DSM) is compensated, and the locking problem caused by large sampling voltage fluctuation is solved. Meanwhile, a voltage shifting technique is introduced to adjust the locked voltage region of differential sampling PD (DSPD), which can improve the linearity of DSPLL for better calibration. Fabricated in 65-nm CMOS process, the presented DSPLL achieves measured integrated jitter of 69.09 and 73.26 fs for integer-N and fractional-N modes, respectively. The reference spur is −72.96 dBc, and the worst fractional spur is −55.26 dBc. The total power consumption is 19.2 mW at a 1.2-V supply, achieving a figure of merit jitter (FOMJ) of −249.9 dB.

This paper presents an integer-N sampling phase-locked loop (S-PLL) characterized by both low jitter and low spur. The design integrates a high-gain double-edge sampling phase detector (PD) and a self-retimed multi-modulus divider (MMD) aimed at mitigating the in-band noise. Furthermore, it features a compact implicit common-mode voltage-controlled oscillator (VCO) with a second harmonic tuning tailored for noise reduction. The proposed S-PLL, fabricated in a 28-nm CMOS technology, operates at 31 GHz with a 250-MHz reference. The measured RMS jitter is 39.69 fs integrated from 10 kHz to 100 MHz, with a reference spur of −63.2 dBc. The proposed PLL achieves a figure-of-merit (FoM) of −253.6 dB with a 28-mW power and a 0.047-mm2area.

This paper reports a reference-less frequency- detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 [(Gb/s)/$\mu \text{s}$] and an energy efficiency of 1.3 pJ/bit.

This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is <; 0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UIpp jitter tolerance up to 10 MHz for all the three modes.

This paper provides an in-depth analysis of the third-order bang-bang clock and data recovery (BBCDR) circuit, which accurately predicts its operating characteristics, namely, the jitter transfer function (JTF), the jitter tolerance (JTOL), and the jitter generation (JGEN). By formulating the time-domain waveforms, we introduce a characterizing method and also derive the closed-form equations and their simplified versions under specific conditions, which are related with the second-order loop filter (LF). Our framework is consistent with the conclusions of the prior works. Also, we discuss through the time-domain behavior, the sinking area of the JTOL and other specific phenomenon appearing in the third-order BBCDR loop. We verify all above prediction by system-level simulations with the MATLAB/simulink model.