Utilization of the Delay-Doppler (DD) domain enables the recently proposed two-dimensional (2D) Orthogonal Time Frequency Space (OTFS) waveform to provide consistent performance under high mobility communication systems. OTFS outperforms existing standard waveforms under such time-frequency selective channels, making it a waveform candidate for future wireless communication systems. In this work, we present an implementation of an OTFS waveform-based system on a Universal Software Radio Peripheral (USRP) X310 Software Defined Radio (SDR). This system is tested in a realistic indoor office environment at a 5 GHz carrier frequency band with 150 MHz bandwidth. The resulting constellation diagrams were observed for BPSK, 4-QAM, and 16-QAM modulated OTFS symbols. Furthermore, for 4-QAM symbols, several communication metrics, such as Bit Error Rate (BER) and Error Vector Magnitude (EVM), were evaluated against different gains at the USRP. The resulting constellation diagrams, BER, and EVM graphs show a successful implementation of our OTFS system.

Localization will be an essential requirement for various$6^{\text{th}}$generation (6G) communication system applications. Integrated Sensing and Communication (ISAC) is seen as a key enabling technology that can provide the capability of combined communication and localization. Reliable ISAC in a high-mobility environment can be challenging and existing communication waveforms suffer from severe degradation due to significant Doppler effect. The Delay-Doppler (DD) domain can be commonly seen in the results of Radio Detection and Ranging (RADAR) systems, which is the baseline for Orthogonal Time Frequency Space (OTFS) modulation. Due to the information encoding in DD domain, OTFS shows significant resilience against doubly-selective channels. In this work, we report the sensing functionality performance of our complete sub-6GHz ISAC system based on the OTFS waveform, implemented on a USRP X310 Software Defined Radio (SDR). The sensing capability of the system is experimentally verified in both an anechoic chamber and in an office scenario for single and for multitargets.

This paper presents a millimeter-wave (mmWave) integrated communication and sensing (ICAS) system with softwaredefined radio (SDR) that can support two-stream multiple-input multiple-output (MIMO) communication and mono- as well as bi-static sensing. The system consists of a ZCU111 evaluation board with a high-performance radio-frequency system-on-chip (RFSoC) field-programmable gate array (FPGA) and two 60 GHz dual antenna beamforming modules. The SDR design comprises 4 digital-to-analogue and 4 analogue-to-digital converters with dedicated memories and a programmable sampling frequency in the 160-4000 MHz range with 160 MHz step-size. The RF frontends support an instantaneous bandwidth of up to 2 G H z, and a 90° horizontal beam scan. The sensing function is demonstrated using a typical frame-based orthogonal frequency division multiplexing (OFDM) communication signal. A range resolution of 6.7 cm and an angular resolution of 1.45° is achieved.

The proposed demonstration shows a real-time integrated communication and sensing (ICAS) system, operating in the millimeter-wave (mmWave) frequency band at a center frequency of 60 GHz. The demonstrated system allows bidirectional data communication with a coded data rate of up to 2.6 Gbit/s as well as mono-static radio detection and ranging (RADAR) with a range resolution of 6.7 cm and up to 2.1 kHz sensing rate. According to the basic principles of ICAS, the same hardware resources, the same signal waveform and the same frequency channel are used for both communication and sensing. All necessary functionality and the whole digital signal processing is integrated in one system-on-chip, resulting in a small form factor of the transceiver stations.

The unified 3D communication networks, integrating standard terrestrial mobile communication networks and non-terrestrial networks (NTNs), are seen as the key enabler for global connectivity in the next generation (6G) wireless communications. To achieve this goal, new technologies and components are needed in order to meet the requirements for the 6G networks in terms of higher data rates, and enhanced reliability, security and network reconfigurability. This work introduces the German project 6G-TakeOff, aimed at the design of solutions for unified 3D networks for 6G wireless communication systems. The project consortium brings together academic and industrial partners from Germany and Europe, covering the entire value chain from design of electro-nics to applications. This work presents the key hardware components required for 3D networks and the concept for demonstration of their functionality.

The performance of practical millimetre wave (mmWave) communication systems is affected by different hardware impairments. This can significantly impact the channel reciprocity-based physical layer security (PLS) methods. This paper studies the impact of in-and quadrature-phase (IQ) imbalance on the physical layer secure key generation algorithm performance. Numerical analysis is performed in MATLAB by modelling and simulating the IQ imbalance, which is then applied to the 60 GHz channel used to generate secret keys. The study's outcome shows that IQ imbalance increases bit mismatches up to an average of 5% for an amplitude imbalance of 1.4 dB and a phase imbalance of 7°. However, additional iterations of parity bit sequence exchanges can recover these in the reconciliation phase. As a result, the information is slightly more exposed to an eavesdropper.

This paper introduces the concept of optimizing beam training at the medium access control (MAC) layer by employing passive sensing. The environment information can be extracted from the channel state information (CSI) when data frames are received. The delay and angle of arrival (AoA) parameters are estimated assuming an orthogonal frequency-division multiple (OFDM) system operating in the 60 GHz band. A method for enhancing the communication performance on the MAC layer by using sensing information from multiple wireless transceivers is proposed.

This paper proposes modifications for the parallel sequence spread spectrum (PSSS) modulation scheme, which improve the bit error rate (BER) performance and peak-to-average power ratio (PAPR) at the same time. In our scheme, some data bits are encoded as phase shifts of the spreading sequences. Thus, the number of transmitted sequences can be reduced, and the resulting PAPR is lowered. The improvements proposed here are inspired by code shift keying (CSK) and parallel combinatory spread spectrum (PCSS) systems. The PSSS variant investigated here is based on recently discovered real-value spreading sequences, where all sequence coefficients are defined in the real domain.

This paper proposes an optimized pipelined decoding architecture with seven processing stages for unrolled LDPC decoders. Pipelined design with seven register layers significantly increases the resulting clock frequency. Moreover, we investigate the optimal layout shape for unrolled decoders. This paper's fastest decoder is based on the IEEE 802.11n LDPC(1944,1620) parity-check matrix and achieves 2937 Gb/s of coded throughput after physical design. By optimizing the pipeline, floorplan, and employing a codeword length of 1944 bits, we increased the throughput by 241% compared to the previous fastest LDPC decoder presented in the literature. To the best of our knowledge, it is the fastest soft-decision decoder published so far. The standard min-sum approach is employed for decoding, and the proposed improvements consider changes only on the hardware level.

This paper compares three hardware variants of successive cancelation (SC) decoders for polar codes. The fastest implementation, based on the basic SC, provides decoding throughput up to 1700 Gb/s, when implemented in a 28 nm CMOS technology at the worst-case timing corner. This is the fastest polar decoder published so far, to the best of our knowledge. We also discuss the difficulties of implementing single-parity-check nodes and repetition nodes in fast simplified SC (Fast-SSC) decoding algorithm. These two node types are the primary sources of clock frequency reduction, and special care needs to be taken when these elements are implemented. The Fast-SSC decoder requires ~3 times fewer hardware resources than the base version of SC, but achieves ~10% lower decoding throughput.

This paper reports our latest implementation results of a fully unrolled LDPC decoder prototyped in 28 nm CMOS technology. The decoder achieves 1218 Gbps coded throughput and consumes a 5.49 mm2chip area. The standard min-sum decoding algorithm with four-bit quantization, five unrolled iterations, (648,540) parity matrix, and a seven-stage pipeline is employed. Such implementation achieves a higher data rate than adaptive degeneration and finite-alphabet decoding algorithms, requires less silicon than the solutions mentioned above, and is fully compliant with the IEEE 802.11n WLAN standard.

In this work, we propose a Deep neural network-assisted Particle Filter-based (DePF) approach to address the Mobile User (MU) joint synchronization and localization (sync&loc) problem in ultra-dense networks. In particular, DePF deploys an asymmetric time-stamp exchange mechanism between the MUs and the Access Points (APs), which, traditionally, provides us with information about the MUs’ clock offset and skew. However, information about the distance between an AP and an MU is also intrinsic to the propagation delay experienced by the exchanged time-stamps. In addition, to estimate the angle of arrival of the received synchronization packets, DePF draws on the multiple signal classification algorithm that is fed with the Channel Impulse Response (CIR) experienced by the sync packets. The CIR is also leveraged to determine the link condition, i.e. Line-of-Sight (LoS) or Non-LoS. Finally, to perform joint sync&loc, DePF capitalizes on particle Gaussian mixtures that allow for a hybrid particle-based and parametric Bayesian Recursive Filtering (BRF) fusion of the aforementioned pieces of information and, thus, jointly estimates the position and clock parameters of the MUs. The simulation results verify the superiority of the proposed algorithm over the state-of-the-art schemes, especially that of the extended Kalman filter- and linearized BRF-based joint sync&loc. In particular, only drawing on the synchronization time-stamp exchange and CIRs from a single AP, for 90% of the cases, the absolute position and clock offset estimation error remain below 1 meter and 2 nanoseconds, respectively.

This paper investigates coding and modulation schemes for wireless communication based on variable-rate parallel sequence spread spectrum (PSSS). PSSS can adapt the spreading gain according to channel conditions. When this modulation technique is combined with external forward error correction (FEC), a challenge arises in adjusting the gains from FEC and PSSS to achieve the highest spectral and energy efficiency. We profile the bit error rate (BER) and energy efficiency as a function of the signal-to-noise ratio (SNR) for PSSS combined with low-density parity-check (LDPC) codes implemented in 28 nm CMOS technology. This analysis reveals that the gain provided by PSSS should be used only in exceptional cases, whereas LDPC codes provide the gain at a lower spectral- penalty. Moreover, we simplify our system by reducing the number of LDPC code rates. As compared to IEEE 802.11n, we exclude the 2/3 and 3/4 FEC code rates from the hardware and compensate these modes by using the variable-rate PSSS.

This paper investigates chip area, clock frequency, throughput, power consumption, and energy efficiency of real-valued spreading sequences proposed for Parallel Sequence Spread Spectrum (PSSS). On the one hand, real-valued sequences cause significant hardware overhead when compared to the usually employed binary m-sequences. On the other hand, these sequences achieve 2.5 dB better signal-to-noise ratio (SNR) performance in PSSS systems. The experiments performed on the test designs implemented in a 28 nm CMOS technology reveal that the real-valued sequences, up to the length of 17 bits, cause low hardware overhead and allow processing data streams up to 400 Gbps. Longer sequences can break the barrier of 1 Tbps, but this is paid with a large chip area and extremely high power consumption. In the case of a 1 Tbps PSSS system, power dissipation is the main critical parameter in need of optimization.

In this work, we study the joint synchronization and localization (sync&loc) of Mobile Nodes (MNs) in ultra dense networks. In particular, we deploy an asymmetric time-stamp exchange mechanism between the MNs and the Access Nodes (ANs), that, traditionally, provides us with information about the MNs' clock offset and skew. However, information about the distance between an AN and a MN is also intrinsic to the propagation delay experienced by exchanged time-stamps. In addition, we utilize Angle of Arrival (AoA) estimation to determine the incoming direction of time-stamp exchange packets, which gives further information about the MNs' location. Finally, we employ Bayesian Recursive Filtering (BRF) to combine the aforementioned pieces of information and jointly estimate the position and clock parameters of the MNs. The simulation results indicate that the Root Mean Square Errors (RMSEs) of position and clock offset estimation are kept below 1 meter and 1 nanosecond, respectively.

In this work, we propose a hybrid Bayesian approach towards clock offset and skew estimation, thereby synchronizing large scale networks. In particular, we demonstrate the advantage of Bayesian Recursive Filtering (BRF) in alleviating time-stamping errors for pairwise synchronization. Moreover, we indicate the benefit of Factor Graph (FG), along with Belief Propagation (BP) algorithm in achieving high precision end-to-end network synchronization. Finally, we reveal the merit of hybrid synchronization, where a large-scale network is divided into local synchronization domains, for each of which a suitable synchronization algorithm (BP- or BRF-based) is utilized. The simulation results show that, despite the simplifications in the hybrid approach, the Root Mean Square Errors (RMSEs) of clock offset and skew estimation remain below 5 ns and 0.3 ppm, respectively.

Millimeter wave (mmWave) communication has emerged as a key technology for achieving high data throughput and low latency in 5G networks. Thanks to the large channel bandwidths in the mmWave spectrum (e.g. 2.16 GHz in the 57-66 GHz band), mmWave technology allows precise and accurate time of flight (ToF) measurements, hence supporting precise and accurate positioning. In this paper, an experimental evaluation of ToF-based localization in the 60 GHz band is presented. We implemented the two-way ranging (TWR) protocol between a mobile node and multiple anchor nodes. The implementation is carried out on an own software-defined radio (SDR) baseband platform, combined with commercial 60 GHz chipsets. Tests were performed indoors in a laboratory environment. The results of our evaluation show that a positioning error of less than 5 cm can be obtained.