Demo Data from VLDB 2026 / reviewers in the wild / expert
Iiro Hartimo
dblp:25/146
· DBLP profile ↗
8ranked-venue papers
3as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 5 · 1 first-authorSystems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 60% Integrated circuit design · 23% Hardware accelerators and domain-specific architectures · 18% | |
| Theoretical computer science
1 paper |
Mathematical optimization · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
dataflow architecture |
0.0 | 1 | 1986 | DFSP: A Data Flow Signal Processor · IEEE Trans. Computers 1986 |
Integrated circuit design
digital signal generation |
0.0 | 1 | 1979 | Comments on "A Stable, Two-Multiplies-per-Cycle Algorithm for Digital Generation of Sinusoids in Real Time" · IEEE Trans. Computers 1979 |
Hardware accelerators and domain-specific architectures
signal processing accelerator |
0.0 | 1 | 1986 | DFSP: A Data Flow Signal Processor · IEEE Trans. Computers 1986 |
Mathematical optimization › numerical analysis
numerical stability |
0.0 | 1 | 1979 | Comments on "A Stable, Two-Multiplies-per-Cycle Algorithm for Digital Generation of Sinusoids in Real Time" · IEEE Trans. Computers 1979 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0roundoff error analysis · 0.0recursive algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Roundoff noise minimization in a direct form delta operator structureabstractDelta operator realizations of IIR filters have received a lot of interest due to their good finite-wordlength properties. We present a detailed analysis of the computationally efficient transposed direct form II delta structure, which is also known to have excellent roundoff noise performance under fast sampling. The focus is on the roundoff noise minimization in fixed-point implementations. The free /spl Delta/ parameter in the delta operator is optimized with respect to the output roundoff noise within the scaling constraints. Moreover, the required internal wordlength to obtain a prespecified noise performance is derived. Juha Kauraniemi, Timo I. Laakso, Iiro Hartimo, Seppo J. Ovaska |
ICASSP | 3 |
| 1993 | Systolic Array for 2-D Circular Convolution Using the Chinese Remainder Theorem
Iiro Hartimo |
ISCAS | 2 |
| 1991 | General criterion for the absence of limit cycles in filter structures with a single quantizerabstractA criterion for the absence of zero-input limit cycles in recursive digital filter structures that can be implemented with a single quantizer in the recursive loop is presented. The criterion can be applied with a rounding or with a magnitude truncation quantizer and accounts for the use of error feedback as well. Additionally, a criterion for the elimination of constant-input limit cycles is formulated. The criteria are applied to several well-known filter structures. Since most of the structures have previously been analyzed in a multiquantizer implementation only, new results on their stability properties in the single-quantizer configuration are obtained.> Timo I. Laakso, Paulo S. R. Diniz, Iiro Hartimo |
ICASSP | 3 |
| 1991 | Error feedback for floating-point cascade-form digital filtersabstractThe authors propose the use of error feedback for roundoff noise reduction in cascade-form recursive digital filters employing floating-point arithmetic. The floating-point error feedback has a similar mechanism to the fixed-point error feedback. However, the optimal error feedback solution (in the sense of minimum mean-square error) for the floating-point case is different from the corresponding fixed-point case. The formulated optimal feedback coefficients are shown to be independent of the section of ordering and zero-pole pairing, which does not hold in the fixed-point case. Finally, a suboptimal error feedback is proposed and shown to provide a constant output SNR (signal-to-noise ratio) independent of the specific characteristics of the filter except the filter's order. Several examples are given to verify these results.> Bing Zeng 0001, Timo I. Laakso, Iiro Hartimo, Yrjö Neuvo |
ICASSP | 3 |
| 1986 | DFSP: A Data Flow Signal ProcessorabstractThe concept of data flow computing is applied to digital signal processing (DSP). A data flow signal processor (DFSP) architecture is presented. The principles of data flow computing are carefully considered in order to conform with the special properties of DSP. The bus oriented architecture is easily configured to meet various performance requirements. The DFSP architecture is most suitable for nonrecursive algorithms. Typical tasks of this nature are transforms and FIR filters. A simulation model of the DFSP architecture has been developed. Simulation results of two application examples are given. Iiro Hartimo, Klaus Kronlöf, Olli Simula, Jorma Skyttä |
IEEE Trans. Computers | 1 |
| 1983 | Self-sustained stable oscillations of second order recursive algorithmsabstractRecursive computation can be used to generate sine waveforms. The waveforms are degraded by the round-off noise caused by rounding the results of multiplications. The variance of the round-off noise will increase during the computation if white noise model is assumed. However, in certain cases this will not happen. In this paper the so called 'locking' phenomenon is described. A measure is given to the locking sensitivity of a certain algorithm. Some results of computer simulations and hardware measurements are also given. Iiro Hartimo |
ICASSP | 1 |
| 1982 | Performance of an experimental data flow architecture for signal processingabstractA new architecture based on the data flow principle has been developed for signal processing purposes. The Data Flow Signal Processor (DFSP) is capable of highly parallel computation of block realizations of nonrecursive algorithms. The flexibility and modularity of the DFSP architecture are illustrated by two examples. The three-sensor problem shows the high performance of the DFSP in handling three 100 kHz input streams and performing correlation computations on them. The second example shows that 256 × 256 images can be processed with spatially restricted operations at video rate. Klaus Kronlöf, Jorma Skyttä, Iiro Hartimo, Olli Simula |
ICASSP | 3 |
| 1979 | Comments on "A Stable, Two-Multiplies-per-Cycle Algorithm for Digital Generation of Sinusoids in Real Time"abstractRecently, Silverston1has given an algorithm to produce sinusoids with only two multiplications per cycle. With a simple substitution the algorithm can be further changed to have only one multiplication per cycle. The stability of these recursive algorithms depends on the roundoff errors and it cannot be stated straightforward. Iiro Hartimo, Leo Ojala |
IEEE Trans. Computers | 1 |