We present a new traffic dataset, Meteor, which captures traffic patterns and multi-agent driving behaviors in unstructured scenarios. Meteor consists of more than 1000 one-minute videos, over 2 million annotated frames with bounding boxes and GPS trajectories for 16 unique agent categories, and more than 13 million bounding boxes for traffic agents. Meteor is a dataset for rare and interesting, multi-agent driving behaviors that are grouped into traffic violations, atypical interactions, and diverse scenarios. Every video in Meteor is tagged using a diverse range of factors corresponding to weather, time of the day, road conditions, and traffic density. We use Meteor to benchmark perception methods for object detection and multi-agent behavior prediction. Our key finding is that state-of-the-art models for object detection and behavior prediction, which otherwise succeed on existing datasets such as Waymo, fail on the Meteor dataset. Meteor is a step towards developing more sophisticated perception models for dense, heterogeneous, and unstructured scenarios.

This paper explores the design of efficient capacity achieving polar codes for multiple input multiple output (MIMO) channels and schemes for polar coded spatial multiplexing (PCSM). For polar code construction, the singular value decomposition (SVD) of a given MIMO channel into multiple independent single input single output (SISO) channels is considered as the first step of natural polarization. Firstly, we propose a basic PCSM scheme by constructing a polar code for each independent SISO channel. Then, we extend the scheme by using compound polar codes to construct a unified PCSM scheme for MIMO channels. Further, we present a novel approach for constructing an optimal compound polar codes which minimize block error rate (BLER) for a given NR× NTMIMO channel. Simulation results reveal that the extended schemes achieve at least 1.5 dB gain in terms of BLER with lesser computational complexity as compared to the basic scheme.

. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against the simple deterministic high-level specification of the entire system. Our verification methodology, based on Symbolic Trajectory Evaluation, is able to bridge the wide gap between the abstract specification and the implementation specific details of the subsystem. This paper presents a detailed description of an industrial application of this methodology to the fixed point execution unit of the PowerPC processor. We were able to verify a representative instruction under all possible stall, bypass, pipeline conditions and under all possible timings for interface to other functional units in the processor. 1. Introduction Some modern systems with a simple deterministic high-level specification have implementations that exhibit highly nondeterministic behaviors. A large class of systems that exhibit such...

Our goal is to transform a low-level circuit design into a more abstract representation. This is done in two stages. Tranalyze, an existing analysis tool, takes a switch-level circuit and generates a functionally equivalent gate-level representation. The thesis focuses on the second stage, which takes a gate-level sequential circuit and performs a temporal analysis that abstracts the clocks from

The paper describes a new technique for extracting clock level finite state machines (FSMs) from transistor netlists using symbolic simulation. The transistor netlist is preprocessed to produce a gate level representation of the netlist. Given specifications of the circuit clocking and input and output timing, simulation patterns are derived for a symbolic simulator. The result of the symbolic simulation and extraction process is the next state and output function of the equivalent FSM, represented as Ordered Binary Decision Diagrams. Compared to previous techniques, our extraction process yields an order of magnitude improvement in both space and time, is fully automated and can handle static storage structures and time multiplexed inputs and outputs

We look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion operation. The library is specified as a set of allowed permutations of phase assignments on each base function. Traditional approaches to this problem have been limited to greedy heuristics based on local information. Our approach takes a more global view and maps the problem of inverter minimization into a problem of removing a minimum of vertices from a graph, so as to make the remaining graph two-colorable. This approach has the flexibility of capturing a variety of design-specific features that are relevant to the problem of inverter minimization. Although, in general the problem is NP-complete, we have developed several good heuristic and branch and bound search techniques.

In this paper, we present a framework for performing switchlevel simulation on hardware accelerators.A symbolic analyzer preprocesses the MOS network into a functionally equivalent Boolean representation.The analyzer thus converts switch-level simulation into a task of evaluating Boolean expressions.Our approach maps the Boolean representation into the instruction set of the hardware accelerator.The resultant framework supports switch level simulation on a class of hardware accelerators that traditionally have been limited to gate-level simulation.1.