With more degrees of freedom in the along-track axis, multichannel SAR systems are widely investigated for the purpose of ground moving target indication and motion parameter estimation. However, since conventional multichannel SAR system usually works at the side-looking mode and only the radial velocity is considered, it fails to detect targets only moving in azimuth. In this paper, the variable-boresight configuration is designed for multichannel SAR and overlapping imaging mode is applied to detect targets moving in azimuth. Besides, this system can also provide the precise velocity information of the moving target. Finally, the effectiveness of the proposed approach is verified with simulated multichannel SAR data.

This paper presents a new scheme for moving target velocity estimation in conventional high-resolution wide-swath (HRWS) SAR systems. A generalized steering vector is designed for azimuth ambiguity suppression and the velocity parameter of the moving target is involved in this modified steering vector. The low PRF in HRWS-SAR systems will result in serious azimuth ambiguity. When the adopted parameter is matched with the real velocity of the moving target, its azimuth ambiguities will be suppressed clearly. Entropy can be used to measure the performance for azimuth ambiguity suppression. The velocity can be estimated through searching the matched velocity. Finally, the effectiveness of the proposed approach is verified by simulated multichannel SAR data.

This letter presents a new scheme for ground moving target indication in high-resolution wide-swath (HRWS)-synthetic aperture radar (SAR) systems. The asymmetry of the Doppler spectra is measured to extract the range bins with moving targets. To improve the computational efficiency, only the extracted range bins are used to restore the unambiguous Doppler spectra. The two-look processing technique is then applied to generate two looks and moving targets are indicated by comparing the difference between the two looks. In this detection scheme, the configuration of the conventional HRWS-SAR system remains unchanged and no additional receiving channels are needed. The experimental results show the effectiveness of this detection scheme.

In this paper, a new scheme is presented for ground moving target indication for multichannel synthetic aperture radar (SAR) systems using the asymmetric distribution of the spatial spectrum. Two feature images are generated via accumulating energy intensities of the positive and the negative spatial spectrum, respectively. In the two images, the stationary backgrounds have the same intensity while moving targets are not due to their across-track velocities. Coherent subtraction is carried out to implement clutter suppression and potential moving targets can be indicated through the constant-false-alarm-rate (CFAR) test. When dealing with slow weak moving targets, this developed approach can still obtain good detection performance. Finally, the effectiveness of the proposed approach is verified by real airborne SAR data.

This paper mainly simulated the single event latch-up (SEL) for the CMOS inverter under the 0.18um technology. The SEL of integrated circuit (IC) was also analyzed in detail. The result showed that the parasitic lateral transistors NPN and PNP of NMOS and PMOS play a role in the SEL happening process. The changes of the drain voltage and the drain current and the functional failure of the circuit were also explained in further. Therefore the new SEL model could be established.

The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current. The origin model was improved based on the simulated results. The result studying the improved latch up model shows that the smaller ratios of the internal parasitic resistors between RW1and RW2or RS1and RS2could lead to smaller latch up current and delay more time for the latch up occurrence.

This paper presents an improved tool called FITVS (Fault Injection Tool for Validating SEE) using the FPGA-based emulation system for fault grading. A novel library-replace-modeling technique that can quickly and easily perform SEE by injecting faults into the circuit nodes is proposed. It helps IC designers to enhance the quality of their design by providing the sensitivity information of all nodes. Also the fault injection effectiveness is improved with relative to the traditional methods by utilizing C# program and FPGA emulation, and the speed of injection can reach the order of lus/fault.