The COVID-19 pandemic has caused both significant disruption and catalysed extensive experimentation in how education has been and may be delivered worldwide. The discipline of computing has been part of this experimentation, and significant innovations have been implemented and disseminated. Furthermore, educational provision and learner expectations may have evolved in response to the experiences during the pandemic; whilst still subject to disruption, higher education in many jurisdictions is still returning to a new (ab)normal. In the UK, whilst there has been a return to traditional face-to-face delivery, one estimate suggests that nearly a third of courses continue to involve some hybrid learning as opposed to about 5% before the pandemic. Learners' preferences for delivery approach remains critical and has been explored in previous work predominately by survey-based approach. This single UK institutional case study explores learner preferences by using workshops (N=45 students across ten workshops) which aspires to co-create an understanding of issues and benefits of the learning, teaching and assessment approaches adopted in the pandemic and identify preferences for future directions. The workshops employed the sailboat retrospective template; they suggest that the preferences are varied but commonly include some face-to-face study and that digital exclusion, social engagement, and motivation/distraction are vital factors to be addressed for further adoption of hybrid or online learning.

Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper describes the project and provides an overview of the research carried out by the TERAFLUX consortium.

Affordable transparent clustering solutions to scale non-HPC applications on commodity clusters (such as Terracotta) are emerging for Java Virtual Machines (JVMs). Working in this direction, we propose the Anaconda framework as a research platform to investigate the role Transactional Memory (TM) can play in this domain. Anaconda is a software transactional memory framework that supports clustering of multiple off-the-shelf JVMs on commodity clusters. The main focus of Anaconda is to investigate the implementation of Java synchronization primitives on clusters by relying on Transactional Memory. The traditional lock based Java primitives are replaced by memory transactions and the framework is responsible for ensuring transactional coherence. The contribution of this paper is to investigate which kind of TM coherency protocol can be used in this domain and compare the Anaconda framework against the state-of-the-art Terracotta clustering technology. Furthermore, Anaconda tracks TM conflicts at object granularity and provides distributed object replication and caching mechanisms. It supports existing TM coherence protocols while adding a novel decentralized protocol. The performance evaluation compares Anaconda against three existing TM protocols. Two of these are centralized, while the other is decentralized. In addition, we compare Anaconda against lock-based (coarse, medium grain) implementations of the benchmarks running on Terracotta. Anaconda's performance varies amongst benchmarks, outperforming by 40 to 70% existing TM protocols. Compared to Terracotta, Anaconda exhibits from 19x speedup to 10x slowdown depending on the benchmark's characteristics.

We compare 15 measures of speech rhythm based on an automatic segmentation of speech into vowellike and consonantlike regions. This allows us to apply identical segmentation criteria to all languages and to compute rhythm measures over a large corpus. It may also approximate more closely the segmentation available to prelexical infants, who apparently can discriminate between languages. We find that withinlanguage variation is large and comparable to the betweenlanguages differences we observed. We evaluate the success of different measures in separating languages and show that the efficiency of measures depends on the languages included in the corpus. Rhythm appears to be described by two dimensions and different published rhythm measures capture different aspects of it. Index Terms: linear discriminant typology acoustic phonetics speech segmentation experimental 1.

In Transactional Memory (TM), contention management is the process of selecting which transaction should be aborted when a data access conflict arises. In this paper, the performance of published contention managers (CMs) is re-investigated using complex benchmarks recently published in the literature. Our results redefine the CM performance hierarchy. Greedy and Priority are found to give the best performance overall. Polka is still competitive, but by no means best performing as previously published, and in some cases degrading performance by orders of magnitude. In the worst example, execution of a benchmark completes in 6.5 seconds with Priority, yet fails to complete even after 20 minutes with Polka. Analysis of the benchmark found it aborted only 22% of all transactions, spread consistently over the duration of its execution. More generally, all delay-based CMs, which pause a transaction for some finite duration upon conflict, are found to be unsuitable for the evaluated benchmarks with even moderate amounts of contention. This has significant implications, given that TM is primarily aimedat easing concurrent programming for mainstream software development, where applications are unlikely to be highly optimised to reduce aborts.

Transactional memory (TM) has become an active research area as it promises to simplify the development of highly scalable parallel programs. Scalability is quickly becoming an essential software requirement as successive commodity processors integrate ever larger numbers of cores. Non-trivial TM applications to test TM implementations have only recently begun to emerge, but have been written in different programming languages, using different TM implementations, making analysis difficult. We ported the popular non-trivial TM applications from the STAMP suite (Genome, KMeans, and Vacation), and Lee-TM to DSTM2, a software TM implementation, and built into it a framework to profile their execution. This paper investigates which profiling information is most relevant to understanding the performance of these non-trivial TM applications using up to 8 processors. We report commonly used transactional execution metrics and introduce two new metrics that can be used to profile TM applications.

Transactional Memory (TM) is receiving attention as a way of expressing parallelism for programming multi-core systems. As a parallel programming model it is able to avoid the complexity of conventional locking. TM can enable multi-core hardware that dispenses with conventional bus-based cache coherence, resulting in simpler and more extensible systems. This is increasingly important as we move into the many-core era. Within TM, however, the processes of conflict detection and committing still require synchronization and the broadcast of data. By increasing the granularity of when synchronization is required, the demands on communication are reduced. Software implementations of TM have taken advantage of the fact that the object structure of data can be employed to further raise the level at which interference is observed. The contribution of this paper is the first hardware TM approach where the object structure is recognized and harnessed. This leads to novel commit and conflict detection mechanisms, and also to an elegant solution to the virtualization of version management, without the need for additional software TM support. A first implementation of the proposed hardware TM system is simulated. The initial evaluation is conducted with three benchmarks derived from the STAMP suite and a transactional version of Lee's routing algorithm.

While Transactional Memory (TM) research on shared-memory chip multiprocessors has been flourishing over the last years,limited research has been conducted in the cluster domain. In this paper,we introduce a research platform for exploiting software TMon clusters. The Distributed Software Transactional Memory (DiSTM) system has been designed for easy prototyping of TM coherence protocols and it does not rely on a software or hardware implementation of distributed shared memory. Three TM coherence protocols have been implemented and evaluated with established TM benchmarks. The decentralized TransactionalCoherence and Consistency protocol has been compared against two centralized protocols that utilize leases. Results indicate thatdepending on network congestion and amount of contention different protocols perform better.

Traditional parallel programming models achieve synchronization with error-prone and complex-to-debug constructs such as locks and barriers. Transactional Memory (TM) is a promising new parallel programming abstraction that replaces conventional locks with critical sections expressed as transactions. Most TM research has focused on single address space parallel machines, leaving the area of distributed systems unexplored. In this paper we introduce a flexible Java Software TM (STM) to enable evaluation and prototyping of TM protocols on clusters. Our STM builds on top of the ProActive framework and has as an underlying transactional engine the state-of-the-art DSTM2. It does not rely on software or hardware distributed shared memory for the execution. This follows the transactional semantics at object granularity level and its feasibility is evaluated with non-trivial TM-specific benchmarks.

Experience in profiling Lee's routing algorithm, a new complex TM application, showed that transactional applications may exhibit dynamic exploitable parallelism, i.e. the amount of useful parallelism available at any point in time varies during the execution of the application. Obviously, executing too many transactions at times when the available parallelism is low will lead to high contention and wasted computation in aborted transactions, and vice versa. Current Transactional Memory (TM) implementations do not account for this behavior.

The contribution of this paper is the first Hardware Transactional Memory (HTM) where the object structure is recognized and harnessed. Our approach is similar to hardware support of paged virtual memory using a virtually addressed cache and a TLB, and is based on a cache hierarchy that allows the addressing of objects by unique object identifiers. The object-aware HTM allows cache overflows of uncommitted data. It also enables a novel commit and conflict detection mechanism. In this preliminary evaluation, the Lee-TM application exhibits overflows that in most previous HTMs would have had to be handled by software, impacting on performance. The simulation provides an insight into the scalability characteristics of the proposed HTM, which uses object and field granularity, lazy versioning and lazy conflict detection. For example, with 32 cores the broadcast of write sets is at under 5% of the bus bandwidth, showing the potential of object-aware HTM systems.

Java program execution times vary greatly with different garbage collection algorithms. Until now, it has not been possible to determine the best GC algorithm for aparticular program without exhaustively profiling that program for all available GC algorithms. This paper presents a new approach. We use machine learning techniques to build a prediction model that, given asingle profile run of a previously unseen Java program,can predict a good GC algorithm for that program. We implement this technique in Jikes RVM and test it onseveral standard benchmark suites. Our techniqueachieves 5% speedup in overall execution time (averagedacross all test programs for all heap sizes) compared with selecting the default GC algorithm in every trial. We present further experiments to show that an oracle predictor could achieve an average 17% speedup on the same experiments. In addition, we provide evidence to suggest that GC behaviour is sometimes independent of program inputs. These observations lead us to propose that intelligent selection of GC algorithms is suitably straight forward, efficient and effective to merit further exploration regarding its potential inclusion in the general Java software deployment process.

Increasing the number of instructions executing in parallel has helped improve processor performance, but the technique is limited. Executing code on parallel threads and processors has fewer limitations, but most computer programs tend to be serial in nature. This paper presents a compiler optimisation that at run-time parallelises code inside a JVM and thereby increases the number of threads. We show Spec JVM benchmark results for this optimisation. The performance on a current desktop processor is slower than without parallel threads, caused by thread creation costs, but with these costs removed the performance is better than the serial code. We measure the threading costs and discuss how a future computer architecture will enable this optimisation to be feasible in exploiting thread instead of instruction and/or vector parallelism.

This article is a case study of the maintenance required to the case base of a commercially fielded case‐based reasoning (CBR) system that provides support for HVAC engineers enabling them to better specify HVAC installations. The article briefly describes the system and details how the case base grew rapidly, causing a problem of case redundancy. A simple algorithm to identify and remove redundant cases is described, along with the results of applying it to the case base. Case obsolescence also was encountered and partially remedied using DBMS techniques. The article analyzes the case‐base maintenance (CBM) required by the system in terms of Richter's knowledge containers and Leake and Wilson's CBM framework and contrasts this case study with experience from NEC and DaimlerChrysler. The article observes that had maintenance of the case base been considered more explicitly during system design and implementation, some of the resulting maintenance would have been unnecessary. The article concludes by identifying lessons learned and highlighting the relationship between the sophistication of the case‐representation and similarity metrics and the ease with which CBM can be undertaken by nontechnical staff. This relationship does not always work in favor of the maintainer.

Cross-linguistic studies of the development of distinctive nasalization show evidence of significant suprasegmental conditioning. Amongst conditioning factors uncovered so far are vowel length and stress. Across languages it is reported that in the related contexts /V:N/ and /VN/, identical except for vowel length, phonologization of nasalization and N-deletion always occur preferentially in the context of long vowels. There is also cross-linguistic evidence of stress-conditioning of distinctive nasalization: nasalization and N-deletion appear to occur preferentially in stressed syllables. In this study, we discuss the results of an experiment designed to measure the possible effects of vowel duration and prominence on the perception of vowel nasalization. Both are seen to have an effect, although in different ways. Results presented here also lend support to the hypothesis that some sound changes, such as those involved in distinctive nasalization, may have a primarily perceptual basis.

No abstract available.

Describes the development of a knowledge-based system (KBS) for predicting strategic maintenance in residential property. An initial feasibility study identified a need for the long-term strategic planning of building maintenance in housing associations. However, conventional maintenance management programs require too much data input, are too inflexible. and do not permit their users to explore potential alternatives. The application of KBS technology to this area directly addresses these problems. This paper examines the need for such systems, and describes the implementation of one such system using a client centred approach to the development of KBSs. The paper concludes by discussing some of the problems that were encountered during the system's development, how they were overcome, and what lessons may be learned for future system developments.>

This paper describes a knowledge analysis tool, ProTest, that assists knowledge engineers structure and validate knowledge. At ProTest's core is a Prolog program that tests elicited knowledge for logical consistency, logical loops, and redundancy. Experience gained from several expert system projects has shown the value of using an intermediate knowledge representation. This can be validated by domain experts before implementation, and then serves as a statement of the knowledge in the system. The intermediate representation that the authors use is inference nets. Practical problems in drawing up inference nets, managing sets of nets and testing sets for consistency, loops, and redundancy led them to design and implement their own tool. They discuss the motivation behind the program, its implementation, its use, and its potential for further development.>

The Flagship project aims to produce a computing technology based on the declarative style of programming. A major component of that technology is the design for a parallel machine that can efficiently utilize the implicit parallelism in declarative programs. The computational models that expose this implicit parallelism are described, and an architecture designed to use it is outlined. The operational issues, such as dynamic load balancing, that arise in such a system are discussed, and the mechanisms being used to evaluate the architecture are described.>