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Sheldon Gilbert

dblp:25/3479 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.011988
An Analog Self-Organizing Neural Network Chip · NIPS 1988
Hardware accelerators and domain-specific architectures › analog computing accelerator
analog neural network		 0.011988
An Analog Self-Organizing Neural Network Chip · NIPS 1988
Hardware accelerators and domain-specific architectures
neural network hardware		 0.011988
An Analog Self-Organizing Neural Network Chip · NIPS 1988

Methods — techniques the papers use, named apart from their topics

self-organizing map · 0.0
YearPublicationVenuePosition
1994 An intermediate frequency modulator using direct digital synthesis techniques for Japanese Personal Handy Phone (PHP) and Digital European Cordless Telecommunications (DECT)
abstract
Transmitters for Japanese Personal Handy Phone (PHP) and Digital European Cordless Telephone (DECT) often use analog I-Q modulators. This paper presents a direct digital synthesis technique suitable for both PHP and DECT applications. Because of the Time-Division-Duplex (TDD) structure of PHP and DECT, transmitter intermediate frequency (IF) signals can be generated at the same frequency as the receiver's IF's. This permits sharing of certain IF filters and reduces transceiver size and weight. A frequency plan that minimizes the digital processing required for the generation of a modulated intermediate frequency carrier is presented. Measured transmitter performance for the PHP is provided. Finally, the complete transmitter is presented as part of a set of integrated circuits for the PHP and DECT.>
Bjorn Bjerede, Joseph Lipowski, James Petranovich, Sheldon Gilbert
 VTC4
1988 An Analog Self-Organizing Neural Network Chip
James R. Mann, Sheldon Gilbert
 NIPS2