Recent research has shown that some defects are detect resilient under normal or high temperature, therefore tests for those defects must be applied under lower temperature. On the other hand, some tests need to be applied under high temperature to improve the detection sensitivity. Thus temperature dependent testing which applies tests at different temperature ranges is needed. This paper discusses and gives a formulation of the temperature dependent test scheduling problem. In the proposed test scheduling scheme, each test is associated with a lower temperature bound and an upper temperature bound to define the temperature range within which the test must be applied. A list schedule based test scheduling algorithm is proposed to find the earliest starting time of each test. Cooling period is inserted when the core temperature is too high and heating sequence is applied when the core temperature is below the required specified temperature for the core. Simulation studies are performed for ITC'02 SoC benchmarks and test scheduling results are shown.

Conventional power constrained test scheduling methods do not guarantee a thermal-safe solution. In this paper, we propose a test scheduling algorithm that satisfies the resource, power, and thermal constraints. First, in contrast to existing schemes, the proposed algorithm exploits superposition principle to perform fast and accurate thermal simulation, which, in turn, allows the algorithm to search for solutions which introduce cooling periods between tests to reduce the overall test length. Second, we propose a test partition-based method to further improve the performance of the test scheduling. We apply our test scheduling algorithm to ITC'02 SoC benchmarks and the results show considerable improvement in the total test length over existing methods.

For core-based system-on-chip (SoC) testing, conventional power-constrained test scheduling methods do not guarantee a thermal-safe solution. Also, most of the test scheduling schemes make poor assumptions about power consumption. In deep submicron era, leakage power and wake-up power consumption can not be neglected. In this paper, we propose a partition based thermal-aware test scheduling algorithm with more realistic assumptions of recent SoCs. In our test scheduling algorithm, each test is partitioned and the earliest starting time of each partition is searched. To reduce the execution time of thermal simulation, we also exploit superposition principle to compute the power and thermal profile rapidly and accurately. We apply our test scheduling algorithm to ITC'02 SoC benchmarks and the results show improvements in the total test time over scheduling schemes without partitioning.

We propose a test scheduling algorithm that ensures the resource compatibility and satisfies both power and thermal constraints. The proposed algorithm can start a test at an arbitrary time and it has the capability of delaying a test to let a core cool down to find a valid schedule even when traditional scheduling schemes cannot find a solution. To reduce the execution time of thermal simulation, we exploit superposition principle to compute the thermal profile rapidly and accurately. We apply our scheduling algorithm to ITC'02 SoC benchmarks and the results show a remarkable improvement in the total test length over other methods, while meeting the thermal and power constraints.