We present a high-frequency impedance extraction method for horizontal interconnects as needed in 3-D integrated circuits (ICs), where the horizontal interconnects are sandwiched between substrate layers of possibly different electromagnetic parameters. In particular, for the first time, we develop an extension of the discrete complex images method based on a 2D, or alternatively, 3D magneto-quasi-static (MQS) vector potential Green's functions to extract analytical solutions to the series impedance (resistance and inductance) matrix elements for wire filaments. We then follow standard methods to extract the port impedance. Using the 2D approach, the series impedance per unit length of horizontal wire loops is obtained, which shows excellent accuracy (<; 1% error to Maxwell SV) and significantly improved computational cost (two orders faster than Maxwell SV). Using our 3D approach and combining the series impedance matrix from the MQS extraction engine with the capacitance matrix from an electrostatic extraction engine, we produce an electro-magneto-quasi-static impedance matrix extraction engine, which is used to extract the input impedance of a spiral inductor. In the frequency range spanning near dc to a high frequency cutoff given by four times the frequency of the maximum in the quality factor, we show that our results agree to within less than 5% and 11% deviation to the full-wave simulator HFSS, for the self and mutual loop impedance, respectively. The CPU time using our approach is 18-25× faster than HFSS. These results provide a reasonable foundation for circuit block-level impedance extraction for interconnects and inductors in 3-D integrated systems.

We present an efficient and highly accurate approach to high-frequency impedance extraction for VLSI interconnects and intentional on-chip inductors. The approach is based on a three-dimensional (3D) loop formalism that uses discrete complex images approximations applied to a quasi-magnetostatic treatment of the vector potential, resulting in closed-form expressions for the impedance matrix of current filaments in the presence of a multi-layer substrate. Populating the impedance (Z) matrix for 3D configurations of finite transverse dimensions (including non-Manhattan wires and inductors) is computationally inexpensive, and includes substrate eddy current effects that become quantitatively important in the frequency regime beyond 20 GHz which is imminent at the 45 nm technology node onwards. The accuracy, as exemplified by the magnitude of inductor impedance |Z|, is within 5% of a full-wave electromagnetic field solver for frequencies up to 100 GHz, with an order of magnitude lower computation cost. The proposed method represents a core technology for incorporation into system level extraction of analog systems consisting of multiple inductors and nearby interconnects, for CMOS on-chip circuits in the nanometer era.

In the above titled paper (ibid., vol. 28, no. 7, pp. 1047-1060, Jul. 09), there is an error in equation (17) and equation (15) should be modified. The corrections are presented here.

We propose an efficient method to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multilayer conductive substrates. The resulting accuracy (errors less than 3%) and CPU time reduction (more than an order of magnitude) emerge from three different ingredients: a 2-D Green's function approach with the correct quasi-static limit, a modified discrete complex images approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the short distances that are relevant to VLSI interconnects. This approach permits the evaluation of the self-impedance and mutual-impedance of multi-conductor current loops, including substrate effects, in terms of easily computable analytical expressions that involve their relative separations and the electromagnetic parameters of the multilayer substrate.

We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) and CPU time reduction (factors of seven) emerge from three different ingredients: a two dimensional Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a novel discrete dipole approximation to evaluate the magnetic vector potential. This approach permits the evaluation of the mutual impedance between two loops in terms of easily computable analytical expressions that involve the relative separations and the electromagnetic parameters of the multi-layer substrate. The results are valid for long wires, for any separation, and for frequencies up to 100 GHz.

Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This paper provides a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware. First, effects at the micro scale - in interconnects and devices and their implications for performance, reliability and design are discussed. Next, macro scale-circuit and system level issues including substrate temperature gradients as well as strong ET couplings between supply voltage, frequency, power dissipation and junction temperature in leakage dominant technologies are outlined. A recently developed system level ET analysis methodology and tool that comprehends ET couplings in a self-consistent manner and can generate accurate thermal profile of the substrate is summarized. The application of the ET-tool is demonstrated in a number of areas from power-performance-cooling cost tradeoff analysis to circuit optimization, full-chip leakage estimation, and temperature/reliability aware design space generation. Implications of chip cooling for nanometer scale bulk and SOI based CMOS technologies are also discussed. The ET analysis tool is also shown to be useful for hot-spot management. The paper ends with a brief discussion of electrothermal issues in emerging 3D ICs and highlights the advantages of employing hybrid carbon nanotube-Cu interconnects in both 2D and 3D designs.

While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexity of modern systems, software developers are increasingly dependent on specialized development tools such as security profilers, memory leak identifiers, data flight recorders, and dynamic type analysis. Many of these tools require full-system data which covers multiple interacting threads, processes, and processors. Reducing the performance penalty and complexity of these software tools is critical to those developing next generation applications, and many researchers have proposed adding specialized hardware to assist in profiling and introspection. Unfortunately, while this additional hardware would be incredibly beneficial to developers, the cost of this hardware must be paid on every single die that is manufactured.In this paper, we argue that a new way to attack this problem is with the addition of specialized analysis hardware built on separate active layers stacked vertically on the processor die using 3D IC technology. This provides a modular "snap-on" functionality that could be included with developer systems, and omitted from consumer systems to keep the cost impact to a minimum. In this paper we describe the advantage of using inter-die vias for introspection and we quantify the impact they can have in terms of the area, power, temperature, and routability of the resulting systems. We show that hardware stubs could be inserted into commodity processors at design time that would allow analysis layers to be bonded to development chips, and that these stubs would increase area and power by no more than 0.021mm2 and 0.9% respectively.

Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper and thereby extend the lifetime of electrical interconnects. This paper examines the state-of-the-art in CNT interconnect research and discusses both the advantages and challenges of this emerging nanotechnology.

Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability. The work presented in this paper is the first attempt to study the performance benefits of 3-D technology under the influence of such thermal constraints. Using a processor-cache-memory system and carefully chosen applications encompassing different memory behaviors, the performance of 3-D architecture is compared with a conventional planar (2-D) design. It is found that the substantial increase in memory bus frequency and bus width contribute to a significant reduction in execution time with a 3-D design. It is also found that increasing the clock frequency translates into larger gains in system performance with 3-D designs than for planar 2-D designs in memory intensive applications. The thermal profile of the vertically stacked chip is generated taking into account the highly temperature sensitive leakage power dissipation. The maximum allowed operating frequency imposed by temperature constraint is shown to be lower for 3-D than for 2-D designs. In spite of these constraints, it is shown that the 3-D system registers large performance improvement for memory intensive applications.

The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNT-bundle interconnect based on interconnect geometry. Using this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels) is compared to copper wires of the future. It is shown that CNT bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interconnects. The technological requirements necessary to make CNT bundles viable as future interconnects are also laid out.

As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper, for the first time, proposes a systematic methodology to determine a generalized design metric for simultaneously optimizing power and performance in nanometer-scale integrated circuits to achieve design-specific targets while incorporating electrothermal effects. This methodology is shown to provide a more meaningful basis to compare different design choices. The implications of technology scaling and parameter variations on this thermally-aware methodology are also presented.