VLDB 2026 Research / reviewers in the wild / expert
Antara Ghosh
dblp:25/6070
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2008
0000-0003-2349-1642ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Databases, data management, data science and information retrieval · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Integrated circuit design · 13% | |
| Software engineering, system software, and programming languages
1 paper |
Program analysis · 100% | |
| Databases, data mining, and information retrieval
1 paper |
Query processing and optimization · 50% Information retrieval · 50% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Program analysis
model inference |
0.1 | 1 | 2008 | Construction of concrete verification models from C++ · DAC 2008 |
Electronic design automation › hardware verification and test
hardware verification |
0.1 | 1 | 2008 | Construction of concrete verification models from C++ · DAC 2008 |
Electronic design automation › hardware verification and test › formal verification
sequential equivalence checking |
0.1 | 1 | 2008 | Construction of concrete verification models from C++ · DAC 2008 |
Information retrieval › query understanding
query clustering |
0.0 | 1 | 2002 | Plan Selection Based on Query Clustering · VLDB 2002 |
Query processing and optimization › query planning
query plan selection |
0.0 | 1 | 2002 | Plan Selection Based on Query Clustering · VLDB 2002 |
Integrated circuit design › system-on-chip
system-on-chip design |
0.0 | 1 | 2008 | Construction of concrete verification models from C++ · DAC 2008 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | Construction of concrete verification models from C++abstractC++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The challenge of using C++ for sequential equivalence checking comes from two aspects (1) Language constructs such as pointers, polymorphism, virtual methods, dynamic memory allocation, dynamic loop bounds, floating points pose difficulty in creating a model suitable for equivalence checking (2) The memory and runtime required for creating models suitable for equivalence checking from practical C++ designs is huge. Malay Haldar, Saurabh Prabhakar, Basant Dwivedi, Antara Ghosh |
DAC | 5 |
| 2002 | Plan Selection Based on Query Clustering
Antara Ghosh, Jignashu Parikh, Vibhuti S. Sengar, Jayant R. Haritsa |
VLDB | 1 |