This paper presents the design of a wideband pipelined multi-stage noise shaping (MASH) continuous time (CT) delta-sigma modulator (DSM). The quantization error of the overall$1^{\mathrm {st}}$-stage DSM is extracted as the input of the$2^{\mathrm {nd}}$stage, while the outputs of both stages are simply combined without using any digital filters. Overall, different shaping functions are generated for both QN without requiring any digital QN cancellation. Therefore, the pipelined MASH (PMASH) significantly mitigates QN leakage while retaining the decent loop stability of a traditional MASH. Additionally, several analyses have been made for the PMASH topology, e.g. the design guideline, the signal transfer function (STF), the robustness, etc. Clocked at 800MHz and enabling on-chip DAC calibration, the 65nm CMOS prototype with an exemplary 2-2 topology using multi-bit quantizers achieves 82.6 dB SNDR, 98.8 dB SFDR over 15.4 MHz BW at −0.5 dBFS 1.8 MHz input. The power consumption is 16.9 mW with 1.2V/1.5V supplies. It results in a competitive FoM${}_{\mathrm {S\vert SNDR}}$of 172.2 dB, while it avoids any off-chip calibrations.

Conventional noise-shaping (NS) SAR ADCs require a high-quality power supply provided by the power management system consisting of a DC-DC converter and a low dropout (LDO) regulator. However, the LDO’s dropout voltage limits the power system’s efficiency. To enhance efficiency, this paper proposes removing the LDO. Nevertheless, the voltage ripple generated by the DC-DC converter will directly inject into the ADC, causing two issues: 1) ripple modulation with signal, generates modulation tones that affect the linearity, and 2) ripple modulation with shaped-quantization-noise, folding into baseband and increasing in-band noise. To mitigate these errors, we propose a proper frequency management scheme based on oversampling and a low-pass filter (LPF) integrated into the noise transfer function (NTF) of the NS-SAR. This paper implements a 2-channel time-interleaved (TI) NS-SAR ADC with 2nd-order NS and 2nd-order LPF. The prototype, fabricated in a 28nm CMOS process, operates with 1V provided by a boost DC-DC converter with 0.55V input. It achieves an 80-dB-SNDR over a 3-MHz-BW, operating at a sampling rate of 330MS/s with the DC-DC converter switching frequency of 145MHz. The total system consumes 3.59mW, with the ADC itself consuming 3.02mW, and exhibits a Schreier FoM (FoMS) of 170 dB. By removing LDO, the total system efficiency reaches 84.1%.

This paper presents a novel calibration scheme for single-channel SAR, pipelined and pipelined-SAR ADCs using Kolmogorov–Arnold networks (KANs). In the proposed scheme, a multi-sample KAN (MS-KAN) is designed to realize nonlinear code synthesis (NLCS), achieving effective calibration for general nonlinear errors. The MS-KAN-based calibrator can be converted into an analytical expression, making the calibration process transparent, with stronger interpretability, predictability and reliability compared to previous neural network-based calibration algorithms, and assisting in the analysis of ADC nonidealities. Meanwhile, the proposed scheme achieves high calibration performance with low hardware overhead. The proposed scheme also requires much fewer training samples, thereby reducing the effort required for both chip testing and network training. The MS-KAN-based calibrator is verified with two silicon-proven ADCs, a 14-bit 1.3 GS/s pipelined ADC and a 10-bit 700MS/s SAR ADC. Measurement results show that SFDR is improved by 11.5 dB to 30.9 dB after calibration. The quantized calibrators are implemented on both FPGA and 28nm CMOS technology, where a piecewise polynomial (PWP) method is adopted to simplify the implementation of the calibrator. The post-layout simulation results show that the calibrator for the real-time calibration of the pipelined ADC consumes only 6.32 mW, while the calibrator for the SAR ADC consumes 2.42 mW.

This work presents a high energy-efficiency mixed-signal multiply-and-accumulate (MAC) macro in charge-domain for machine learning (ML) systems. It involves crucial features aimed at enhancing energy efficiency, throughput, and area efficiency, namely: 1) a parallel-serial (ParSer) scheme to augment the throughput by parallel input channels and reduce the power via serial analog accumulation rather than digital summation; 2) the weight-independent parallel digital-to-analog converter (DAC) sampling (WIPDS) to cancel weight nonlinearity during sampling and allow for resource-efficient DAC, significantly saving power and area; 3) a high energy-efficiency dynamic amplifier (DA) introduced to improve drivability and counteract attenuation of the serial accumulation, thereby attaining the desired accuracy with relaxed the afterward analog-to-digital converter (ADC) resolution and consequently reducing power consumption; 4) an optimized SAR ADC to reach higher energy efficiency. Fabricated in 28-nm CMOS technology, the prototype exhibits a peak energy and area efficiency of 362 TOPS/W and 3.23 TOPS/mm$^{2}$, respectively.

Many applications of machine learning (ML) have been integrated into edge devices with their low communication latency. In edge computation, the reprocessing of redundant data results in considerable energy waste. The prior research utilized a digital-delta-digital-sigma computing-in-memory (CIM) scheme to mitigate this redundancy. However, the 7-bit LSB-first ADC resulting from the near-zero-mean output distribution led to excessive area and latency overhead. The following digital adder further induced power consumption and latency. We propose a digital-delta-analog-sigma CIM macro incorporating an analog sigma converter (SC) for edge computation, involving a switch-capacitor integrator with a floating inverter amplifier (FIA) and a quantizer. The increased analog swing of the sigma integrator leads to the expanded output distribution, thereby maintaining comparable accuracy with a relaxed quantizer resolution. The simulation demonstrates that our strategy contributes to a 57.5% reduction in latency, a resolution decrease of 2 bits, and better energy efficiency. These improvements can potentially enhance energy efficiency and computational speed in edge computation devices.

The accurate acquisition of farmland information holds paramount importance for effective agricultural resource monitoring and production management. Traditional semantic segmentation methods struggle to perform precise segmentation at the parcel level. Many existing contour extraction methods tend to generate ambiguous and inaccurate outcomes. To overcome these challenges, this article proposes a multiscale edge-guided network for accurate cultivated land parcel boundary extraction, which consists of the following: 1) multiscale guided transformer module: this module is designed to encode parcel features by combining the shunted transformer and atrous convolution modules; it allows for modeling long-distance context and refining features, enabling accurate representation of farmland parcels; 2) edge enhancement module: this module operates on multiscale features during the feature extraction stage, improving the ability to capture fine details and boundaries of farmland parcels; 3) dual-pyramid structure: this structure consists of a bottom-up pyramid that incorporates deformable convolutions; it enhances the accuracy of multiscale object detection, enabling the network to capture features at different levels of detail; and 4) deoverlap operation: this modular is designed to reduce the ambiguity caused by contour overlap in the extracted results. Specifically, the method effectively mitigates the impact of regional, temporal, and background features. The experimental results showcase the attainment of average precision (AP) and mean intersection over union (MIoU) scores of 0.3421 and 85.28, respectively, for the extracted farmland parcels. Moreover, the method yields competitive results across different farmland parcel types, shapes, and temporal intervals. This positions it as a valuable tool for optimizing agricultural production and enhancing resource monitoring capabilities.

The formation of shadows in very high spatial resolution (VHR) remote sensing imagery is attributed to light being blocked by objects, reducing spectral radiance in the shadow landscape. An accurate and robust shadow removal method can recover spectral and textural information and, hence, is a crucial preprocessing step for urban image analyses. In this study, we develop a KnOwledge-driven shadow progressive removal (KO-Shadow) framework with three subnets for VHR imagery using a weakly supervised manner. Specifically, the shadow preelimination subnet is proposed to initially address the large chromatic aberration between the real and shadow situations. Then, the prior knowledge-guided refinement subnet is proposed to refine the preelimination results by mining tone and texture information. Moreover, the locality feature discriminator is designed for region-specific evaluation of the generated shadow-free samples to improve the capacity of subnets. Experimental results of six typical cities in the world show that KO-Shadow is superior to the existing methods. Moreover, the generalizability analysis in complex urban scenarios validates the robustness of our method. The shadow recovery score (SRI) is proposed to evaluate the spectral similarities between the recovered area and shadow-related land-cover types (e.g., road, building, and lawn). The results show that KO-Shadow can yield more visually realistic shadow-free images and better quantitative performance. Overall, KO-Shadow provides a new perspective for VHR image shadow removal by mining the prior knowledge of the complex shadows in urban areas.

This article presents a power-delay-optimized monotonic-specific successive approximation register (SAR) ADC. The SAR feedback loop, comprising the proposed unbalanced N/P-MOS sizing technique, simultaneously reduces the SAR logic delay and the power to overcome the SAR ADC’s speed bottleneck. Benefiting from this technique, the sampling rate of the prototype 10b single channel 1b/cycle SAR ADC reaches 600 and 700 MS/s at 0.9 and 0.95 V supply voltage, while consuming 1.49 and 2.02 mW in 28 nm CMOS, respectively. Moreover, the 10b ADC achieves the SNDR of 56.39 and 56.42-dB at a Nyquist rate input frequency of 600 and 700 MS/s, leading to a Walden FoM of 4.6 and 5.3 fJ/conversion-step, respectively.

This work introduces a two-channel time-interleaved (TI) continuous-time (CT) 3rd-order delta-sigma modulator (DSM). It uses the information from one complete channel to predict the other channel based on the extrapolation principle. Note that, Cascaded Integrator of Distributed Feedforward (CIFF) topology is selected for the loop filter for the following reasons: 1) it could reduce the number of required feedback DACs as much as possible; 2) it allows to implement the zero optimization for the TI DSM such that the performance could be further improved. Furthermore, we employ the technique of error correction to address the issue regarding the delay-free feedback path, which originates from the extrapolating TI DSM. We present the derivations of the target TI CT DSM starting from a single-channel discrete-time (DT) DSM, while the compensation for excess loop delay (ELD) is considered. Fabricated in 65nm CMOS process, this modulator achieves an equivalent output sampling rate of 800MS/s, while the analog channel operates at 400MHz. It exhibits a signal-to-noise and distortion ratio (SNDR) /spurious-free dynamic range (SFDR)/dynamic range (DR) of 75.5dB/89.7dB/79dB over a 10MHz bandwidth. The total power consumption is 33.73mW from 1.2v/1.8v power supplies. It results in a Schreier Figure of Merit (FoM) of 163.7dB based on DR.

This paper presents a continuous-time (CT) 0–4 dual-stage Multi-stAge Noise-sHaping (MASH) Delta-Sigma Modulator (DSM), exhibiting +5dBFS maximum stable amplitude (MSA). In the context of 0–4 MASH topology, the 4-bit CT DSM employed as the second stage only processes 4-bit quantization noise (QN) of the front-end. Though the input signal exceeds the full scale (FS), the second stage still stays stable as long as the signal leakage does not overload it. Such feature guarantees the improved stability over a wider signal input range. In addition, to address the well-known QN leakage issue of MASH topology, we propose to combine the feedforward topology with proportional-integral-based excess loop delay compensation. It ensures high robustness of the proposed 0–4 MASH DSM without requiring any calibration. Additionally, we present an analysis of the anti-aliasing filtering (AAF) for the 0-X MASH DSM. It is found that the overall AAF of the 0-X MASH DSM is contributed from the second stage. Sampled at 400MHz, the 65nm CMOS experimental prototype measures signal-to-noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 76.7dB/87.3dB over a 10MHz bandwidth with 15.1mW power consumption. Moreover, with achieving +5dBFS MSA, the dynamic range (DR) is extended to be as high as 85dB, resulting in a state-of-the-art Scherier Figure of Merit (FoM) of 173.2dB based on DR.

This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.

Shadow detection automatically marks shadow pixels in high-spatial-resolution (HSR) imagery with specific categories based on meaningful colorific features. Accurate shadow mapping is crucial in interpreting images and recovering radiometric information. Recent studies have demonstrated the superiority of deep learning in very-high-resolution satellite imagery shadow detection. Previous methods usually overlap convolutional layers but cause the loss of spatial information. In addition, the scale and shape of shadows vary, and the small and irregular shadows are challenging to detect. In addition, the unbalanced distribution of the foreground and the background causes the common binary cross-entropy loss function to be biased, which seriously affects model training. A contextual detail-aware network (CDANet), a novel framework for extracting accurate and complete shadows, is proposed for shadow detection to remedy these issues. In CDANet, a double branch module is embedded in the encoder–decoder structure to effectively alleviate low-level local information loss during convolution. The contextual semantic fusion connection with the residual dilation module is proposed to provide multiscale contextual information of diverse shadows. A hybrid loss function is designed to retain the detailed information of the tiny shadows, which per-pixel calculates the distribution of shadows and improves the robustness of the model. The performance of the proposed method is validated on two distinct shadow detection datasets, and the proposed CDANet reveals higher portability and robustness than other methods.

In order to improve the feature richness of remote sensing images and meet the needs of remote sensing image interpretation, shadow detection has become a hotspot in high-resolution remote sensing (HSR) research. Traditional threshold-based and machine learning-based methods do show their effectiveness, but they may not take the inherent details of the shadow into consideration, and it is difficult to cope with the saliency and intricate distribution pattern of the shadow in HSR images, which results in the lack of robustness in extracting sufficient global and local shadow contexts. To solve those problems, a top-down contextual saliency detection network (CADNet) is proposed. Compared with the traditional shadow detection network, more contextual information can be retained by the double-branch strategy of the encoder and residual dilation upsampling of the decoder in CADNet. The low-level and high-level semantic information can be combined to accurately predict the salient regions through the proposed short connection. The proposed CADNet is evaluated on a public shadow detection dataset, and the experimental results demonstrate the effectiveness of the proposed CADNet.

With the wide adoption of big spatial data and the emergence of CyberGIS, the nontrivial computational intensity introduced by massive amount of data poses great challenges to the performance of vector map visualization. The parallel computing technologies provide promising solutions to such problems. Evenly decomposing the visualization task into multiple subtasks is one of the key issues in parallel visualization of vector data. This study focuses on the decomposition of polyline and polygon data for parallel visualization. Two key factors impacting the computational intensity were identified: the number of features and the number of vertices of each feature. The computational intensity transform functions (CITFs) were constructed based on the linear relationships between the factors and the computing time. The computational intensity grid (CIG) can then be constructed using the CITFs to represent the spatial distribution of computational intensity. A noninterlaced continuous space-filling curve is used to group the lattices of CIG into multiple sub-domains such that each sub-domain entails the same amount of computational intensity as others. The experiments demonstrated that the approach proposed in this paper was able to effectively estimate and spatially represent the computational intensity of visualizing polylines and polygons. Compared with the regular domain decomposition methods, the new approach generated much more balanced decomposition of computational intensity for parallel visualization and achieved near-linear speedups, especially when the data is greatly heterogeneously distributed in space.