This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

The X-GOLD SDR 2x family of programmable baseband processors is designed for hosting multiple standards of mobile communication, connectivity, and reception of broadcast ser(R) vices. Processors from the X-GOLDw SDR 2x family obtain the necessary flexibility from a set of programmable SIMD (single-instruction, multiple-data) processor cores, which exchange data through shared on-chip memories. The processors are supported by few dedicated configurable hardware accelerators for those DSP tasks which require no or little flexibility, (R) by an ARMW core for the execution of the upper layers of the protocol stack and by standard IO-components.

A hardware implementation of an ADPLL-based clock generator is presented. The digital controlled oscillator (DCO) used in the ADPLL generates a clock signal with a high frequency resolution and a small jitter. The presented ADPLL has a fast acquisition and a large pull-in range. The whole design including the DCO has been described in synthesizable VHDL. It does not contain library specific cells, and can be synthesized independently of the standard cell library. Thus, it is portable and the time required to fit it for different semiconductor processes is reduced considerably. The design adaptation cost is limited to adjustment of a few constants in the VHDL-code. The presented design has been implemented in a V400BG432 VIRTEX FPGA and it has been synthesized using two different standard cell libraries (CMOS AMS 0.6 /spl mu/m and CMOS AMS 0.35 /spl mu/m). The maximum achievable clock frequency is 40 MHz using the FPGA and 52 MHz using the above mentioned standard cell libraries. The maximal lock-in time of the ADPLL is 30 reference clock cycles.