Brain-inspired hyperdimensional computing (HDC) offers much more efficient computing compared to other classical deep learning and related machine learning algorithms. Unlike classical CMOS, emerging non-volatile memories (NVMs) used in the realization of HDC are susceptible to failures under voltage scaling, which is essential for energy saving. Although HDC is inherently robust against errors, this is only possible when hypervectors with a large dimension (e.g., 10,000 bits) are being used, resulting in significant energy consumption. This work demonstrates, for the first time, that different NVM technologies exhibit different error characteristics under voltage scaling. In contrast to conventional CMOS-based SRAM, we demonstrate that the error behavior is data-dependent and not captured by simple bit flips in emerging NVMs. We employ our cross-layer framework that starts from the underlying technology all the way up to the algorithm to develop the novel HDC training approach DropHD. DropHD considerably shrinks the size of hypervectors (e.g., from 10,000 bits down to merely 3000 bits), while maintaining a high inference accuracy. The use of aggressive voltage scaling reduces energy consumption by 1.6 x. DropHD further reduces it to up to 9.5 × while fully recovering the induced accuracy drop, i.e. without a tradeoff.

Hyperdimensional computing (HDC) has been recognized as an efficient machine learning algorithm in recent years. Robustness against noise and simple computational operations, while being limited by the memory bandwidth, make it a perfect fit for the concept of computation in memory (CiM) with emerging nonvolatile memory (NVM) technologies. For an HDC accelerator based on NVM-CiM, there are different parameters from the algorithm all the way down to the technology that interact with each other and affect the overall inference accuracy as well as the energy efficiency of the accelerator. Therefore, in this paper, we propose, for the first time, a full-stack co-optimization method and use it to design an HDC accelerator based on NVM-based content addressable memory (CAM). By incorporating the device manufacturing variability and co-optimizing the algorithm and hardware design, HDC inference on our proposed NVM-based CiM accelerator can reduce the energy consumption by 3.27x, while compared to the purely software-based implementation, the inference accuracy loss is merely 0.125%.

Ternary content addressable memory (TCAM), widely used in network routers and high-associativity caches, is gaining popularity in machine learning and data-analytic applications. Ferroelectric FETs (FeFETs) are a promising candidate for implementing TCAM owing to their high ON/OFF ratio, non-volatility, and CMOS compatibility. However, conventional single-gate FeFETs (SG-FeFETs) suffer from relatively high write voltage, low endurance, potential read disturbance, and face scaling challenges. Recently, a double-gate FeFET (DG-FeFET) has been proposed and outperforms SG-FeFETs in many aspects. This paper investigates TCAM design challenges specific to DG-FeFETs and introduces a novel 1.5T1Fe TCAM design based on DG-FeFETs. A 2-step search with early termination is employed to reduce the cell area and improve energy efficiency. A shared driver design is proposed to reduce the peripherals area. Detailed analysis and SPICE simulation show that the 1.5T1Fe DGTCAM leads to superior search speed and energy efficiency. The 1.5T1Fe TCAM design can also be built with SG-FeFETs, which achieve search latency and energy improvement compared with 2FeFET TCAM.

Emerging devices are susceptible to manufacturing defects due to immature fabrication processes. Ferroelectric field-effect transistors, referred to as FeFETs, are promising emerging devices, but the impact of manufacturing imperfections on these devices has yet to be studied. Thus, we combine a technology CAD (TCAD) model with a fault-injection technique to represent fabrication defects in a FeFET. The TCAD model is calibrated against a fabricated metal-ferroelectric-metal capacitor and uses a multi-domain ferroelectric-layer structure. We address two classes of defects in the ferroelectric layer and map them to stuck-at-fault models referred to as neutral faults (SAP°) and stuck-at-plus and stuck-at-minus (SAP+and SAP−) faults. We also develop a machine-learning (ML) framework to characterize these fault-injected FeFET devices. The ML framework provides a significant speedup in predicting the health of the FE layer as compared to computationally heavy TCAD simulations. Our study of defects in ferroelectric FET (FeFET), which is done for the first time, and the insights gained thereof can provide valuable feedback for the fabrication and yield learning of FeFET-based circuits.

By taking inspiration from the operation of biological brains, emerging brain-inspired hardware has the potential to revolutionize the way computations are performed. Brain-inspired computing can be realized using both classical CMOS and emerging beyond-CMOS technologies, whereas the latter holds the promise to provide substantial energy savings akin to the employment of non-volatile memories. One way to implement highly efficient brain-inspired AI applications is through analog computing schemes, such as Integrate-and-Fire (IF) Spiking Neural Networks (SNNs), which can be implemented using both CMOS and beyond-CMOS technologies as synaptic storage. However, managing the inherent degradation of computing accuracy in analog circuits and mitigating their effects on the predictive accuracy of AI systems remains a key challenge due to the inherent nature of analog computing.In this paper, we discuss how the aforementioned challenges can be addressed. In the first part, we present our SPICE-Torch, a framework that connects low-level SPICE simulations of circuits and memories performing analog computations with high-level accuracy evaluations of NN models based on PyTorch. Furthermore, we present an example of neuromorphic optimization using classical CMOS technology. In the second part, we introduce memristors as an emerging beyond-CMOS technology that can retain their state without any outside influence and are well-suited for brain-inspired neuromorphic hardware. We demonstrate that brain-inspired hardware, realized using classical CMOS or beyond-CMOS technologies, has the potential to revolutionize the way we process information and solve complex computation problems. Nevertheless, to harness its full potential, reliability issues have to be managed carefully and HW/SW codesign is key. Our presented framework SPICE-Torch, which connects low-level SPICE simulations of circuits performing analog computations with high-level accuracy evaluations of NN models based on PyTorch is available as open-source in https://github.com/myay/SPICE-Torch.

Brain-inspired hyperdimensional computing (HDC) is continuously gaining remarkable attention. It is a promising alternative to traditional machine-learning approaches due to its ability to learn from little data, lightweight implementation, and resiliency against errors. However, HDC is overwhelmingly data-centric similar to traditional machine-learning algorithms. In-memory computing is rapidly emerging to overcome the von Neumann bottleneck by eliminating data movements between compute and storage units. In this work, we investigate and model the impact of imprecise in-memory computing hardware, namely TCAM cells, on the inference accuracy of HDC. Our modeling is based on 14nm FinFET technology fully calibrated with Intel measurement data. We accurately model, for the first time, the voltage-dependent error probability in SRAM-based and FeFET-based in-memory computing. Thanks to HDC's resiliency against errors, the complexity of the underlying hardware can be reduced, providing large energy savings of up to 6x. Experimental results for SRAM reveal that variability-induced errors have a probability of up to 39%. Despite such a high error probability, the inference accuracy is only marginally impacted. This opens doors to explore new tradeoffs. We also demonstrate that the resiliency against errors is application-dependent. In addition, we investigate the robustness of HDC against errors with emerging non-volatile FeFET devices instead of mature CMOS-based SRAMs. We demonstrate that inference accuracy does remain high despite the larger error probability, while large area and power savings can be obtained.All in all, HW/SW co-design is the key for efficient yet reliable in-memory HDC for both conventional CMOS technology and upcoming emerging technologies.

The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von Neumann principles. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as a novel structure that offers for the first time disturb-free read operation along with$>\,\,\mathrm {10\,\,\times }$larger memory window (MW) compared to conventional FeFETs. However, all the before-mentioned variations are amplified in such a new structure. This work analyses the impact of temperature variation for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels, and compared to conventional FeFET. Through our cross-layer framework, we demonstrate the severe impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even Hyperdimensional Computing is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level.Hence, investigating and modeling variability effects in a cross-layermanner is indispensable.

Computing the similarity between two binary strings is a frequently used operation in cryptography, machine learning, and other areas. The Hamming distance is a simple yet costly to compute similarity metric. A common way is to XOR both binary input strings and then count the number of 1s. Especially the latter popcount part is inefficient with purely digital circuits. In this paper, a novel analog circuit is proposed to compute the Hamming distance in an ultra-efficient way. Contrary to the major trend in the state of the art, no emerging technology is required. Instead, the unique feature of the mature FDSOI transistor technology is exploited for the first time to perform analog-based similarity calculation. Thanks to the additional back gate available in this technology, the transistor’s threshold voltage can be modulated by more than 1 V. Through this key feature, an ultra-efficient analog computing is realized, replacing the inefficient digital popcount traditionally built from expensive adder tree structures. The design is evaluated with an FDSOI transistor model calibrated with industrial measurements. The energy-delay product is at least 24$\times $smaller than purely digital implementations and the transistor count is reduced by over 2.6$\times $.

In this work, we are the first to investigate and model the characteristics of a commercial 5nm FinFET technology from room temperature (300K) all the way down to cryogenic temperature (10K). We focus on SRAM circuits demonstrating how cryogenic temperatures impact their power, delay, and reliability. SRAM memories are key components in quantum read-out and control circuits, and therefore characterizing their key figure of merits when building cryogenic-CMOS circuits is essential. To achieve that, we first measure the electrical characteristics of nFinFET and pFinFET devices from 300K down to 10K. Then, we carefully calibrate the cryogenic-aware BSIM-CMG, which is the first industry-standard compact model for FinFET technologies designed for cryogenic temperatures. This enables us to reproduce the experimental data in which SPICE simulations come with an excellent agreement with the measurements. Using our well-calibrated transistor models, we simulate a complete 32-bit SRAM memory array, including a write driver, sense amplifier, pre-charger, and output latch. Then, we investigate how cryogenic temperatures impact the SRAM read and write delays at several stages during the operation, as well as the power and energy. For a more comprehensive analysis, we perform our studies for different SRAM types covering high-density, high-performance, and low-voltage cells. All transistor and SRAM analyses are performed at both room temperature and cryogenic temperature to obtain detailed comparisons revealing the exact role that cryogenic temperature plays in SRAMs. All in all, we demonstrate that commercial 5nm FinFET is indeed suitable for cryogenic-CMOS circuits required in quantum processors, revealing that the performance of SRAMs at 10K does improve while power and energy consumption are reduced. Nevertheless, SRAM reliability is more challenging in which noise margins need to be carefully engineered to remain sufficient at 10K.

Hyperdimensional computing (HDC) is an emerging learning paradigm that has gained a lot of attention due to its ability to train with fewer data, lightweight implementation, and resiliency against errors. Similar to the brain, HDC can learn patterns in one iteration from small training data by computing a similarity metric such as Hamming distance. Ferroelectric Field-Effect-Transistor (FeFET) based Ternary Content Addressable Memory (TCAM) has been demonstrated as an excellent candi-date for computing this similarity metric. However, variations in the underlying ferroelectric transistor does impact the reliable HDC operation. In this paper, we demonstrate an end-to-end cross-layer FeFET reliability modeling to obtain robust HDC across the computing stack starting from transistor physics all the way to circuits and systems. The effect of random spatial fluctuation of ferroelectric (FE) domains and other variability sources on electrical characteristics of FeFET is computed through detailed physics-based TCAD simulations. Then, the entire TCAM array is simulated in SPICE using a carefully designed and calibrated compact model to capture the effect of transistor variability on the error probability for individual Hamming distances. Finally, the error probability is employed to compute the loss of inference accuracy of HDC with a language recognition task. We observe very little loss in accuracy even with a high degree of variation.

Specialized hardware accelerators beyond von-Neumann, that offer processing capability in where the data resides without moving it, become inevitable in data-centric computing. Emerging non-volatile memories, like Ferroelectric Field-Effect Transistor (FeFET), are able to build compact Logic-in-Memory (LiM). In this work, we investigate the probability of error (Perror) in FeFET-based XNOR LiM, demonstrating the new trade-off between the speed and reliability. Using our reliability model, we present how Binarized Neural Networks (BNNs) can be proactively trained in the presence of XNOR-induced errors towards obtaining robust BNNs at the design time. Furthermore, leveraging the trade-off between Perror and speed, we present a run-time adaptation technique, that selectively trades-off Perror and XNOR speed for every BNN layer. Our results demonstrate that when a small loss (e.g., 1%) in inference accuracy could be accepted, our design-time and run-time techniques provide error-resilient BNNs that exhibit 75% and 50% (FashionMNIST) and 38% and 24% (CIFAR10) XNOR speedups, respectively.

The era of Big Data, Artificial Intelligence (AI) and Internet of Things (IoT) is approaching, but our underlying computing infrastructures are not sufficiently ready. The end of Moore's law and process scaling as well as the memory wall associated with von Neumann architectures have throttled the rapid development of conventional architectures based on CMOS technology, and cross-layer efforts that involve the interactions from low-end devices to high-end applications have been prominently studied to overcome the aforementioned challenges. On one hand, various emerging devices, e.g., Ferroelectric FET, have been proposed to either sustain the scaling trends or enable novel circuit and architecture innovations. On the other hand, novel computing architectures/algorithms, e.g., computing-in-memory (CiM), have been proposed to address the challenges faced by conventional von Neumann architectures. Naturally, integrated approaches across the emerging devices and computing architectures/algorithms for data-intensive applications are of great interests. This paper uses the FeFET as a representative device, and discuss about the challenges, opportunities and contributions for the emerging trends of cross-layer co-design for CiM.

The rapidly increasing volume and complexity of data is demanding the relentless scaling of computing power. With transistor feature size approaching physical limits, the benefits that CMOS technology can provide is diminishing. For future energy efficient computing systems, researchers aim to exploit various emerging nanotechnologies to replace conventional CMOS technology. In particular, ferroelectric FETs (FeFETs) appear to be a promising candidate to continue improving energy efficiency for data-intensive applications. Advances in FeFET scalability and FeFET compatibility with CMOS have sparked growing interest in device, circuit, and system communities. While FeFET is still evolving, many researchers and developers are already cautiously optimistic about its future. This paper provides a review on FeFET's recent technology advances, challenges, and opportunities, with a particular emphasis upon device modeling and circuit design of FeFET content addressable memory, as well as their applications in machine learning.

Negative Capacitance Field-Effect Transistors (NCFET) are promising significant power reductions while maintaining performance due to their internal voltage amplification. However, the addition of the ferroelectric layer also introduces a higher gate capacitance, which has to be charged and discharged resulting in higher power consumption. This results in trade-offs when employing NC-FinFET with respect to the thickness of the ferroelectric layer and their operating voltage on power, performance and reliability in circuits. This design-space is currently not explored, as existing research focused on a transistor-to-transistor comparison to show the superiority of NC-FinFET at the same voltage. In this work, we evaluate NC-FinFET employment in a full SRAM memory array (including write driver, sense amplifier, pre-charging, etc.) to obtain circuit delay, read and hold power and reliability metrics. This work shows, that solely evaluating SRAM cells results in inaccurate delay and power estimations compared to a full SRAM array. We explore iso-voltage and iso-performance NC-FinFET operation. Additionally, we explore two new operation modes: operating NC-FinFET within the same overall power consumption (iso-power) and operating at the same noise margins (iso-reliability). This exploration shows, for the first time, how ferroelectric layer thickness plays a role on reliability as a 4 nm layer features a 47% loss compared to FinFET. Lastly, we obtain the activity of a register file in a processor simulator to obtain the ultimate impact on power and energy consumption of employing NC-FinFET in a microprocessor.

With the rapid development of emerging technologies, especially the ferroelectric field-effect transistors (FeFETs), the density and energy efficiency of ternary content addressable memory (TCAM) have been increasingly improved. TCAM plays a major role in realizing In-Memory Computing and other brain-inspired computing concepts. Recently, the parallel search functionality of a FeFET based ultra-dense TCAM design is also enhanced with a Hamming distance-based approximate search scheme. However, in order to realize the highly-promising TCAM design, in which the approximate search function based on Hamming distance is implemented, it is inevitable to investigate the impact of temperature on the reliability of FeFET-based TCAM cells as well as all involved peripheral circuits. In this paper, the temperature impact on the FeFET at the device level and the approximate TCAM design at the circuit level is investigated for the first time. The demonstrated example of a FeFET-based TCAM array shows that the unique temperature dependency of a FeFET device can help mitigate the temperature impact on the FeFET TCAM array. Based on the observation, we showcase, evaluate, and discuss in detail one strategy to eliminate the temperature impact on the approximate TCAM design. Understanding and mitigating the deleterious impact of temperature on the reliability of FeFET-based TCAM circuits is essential to ensure reliable In-Memory Computing.

Self-heating is one of the biggest threats to reliability in current and advanced CMOS technologies like FinFET and Nanowire, respectively. Encapsulating the channel with the gate dielectric improved electrostatics, but also thermally insulates the channel resulting in elevated channel temperatures as the generated heat is trapped within the channel. Elevated channel temperatures lowers the performance, increases leakage power and degrades the reliability of circuits. Self-heating becomes worse in each new transistor structure (from planar transistor to FinFET to Nanowire) due to the ever-increasing thermal resistance of the transistor. This leads to elevated temperatures, which must be carefully considered while designing circuits. Otherwise, reliability cannot be ensured. This work presents a self-heating study to illustrate how self-heating matters in digital circuits. It also explores the impact of running workloads in SRAM arrays, such as register files in CPUs, and how self-heating effects in SRAM cells can be mitigated.

The introduction of FinFET technology as an effective solution to continue technology scaling has pushed self-heating effects to the forefront of reliability challenges, especially at the 14nm technology node and below. Due to limited silicon volume for heat dissipation, elevated temperatures across the transistors channel can be generated during operation. This results in a considerable degradation of the key properties of transistors like decreased drain and increased leakage current. In addition, excessive temperatures considerably accelerate aging phenomena in transistors such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), which shorten the lifetime of circuits. In this work, we discuss how self-heating effects in FinFET transistors can prolong the delay of circuits leading to reliability problems. We evaluate self-heating in an entire SRAM block consisting of SRAM cells, pre-charging circuit, sense amplifiers and an output latch. When it comes to reliability and lifetime, we demonstrate how self-heating effects can result in larger aging-induced degradations which, in turn, enforce designers to include wider and wider safety margins to sustain reliability. Lastly, we provide an outlook of self-heating and reliability concerns in Negative Capacitance Field Effect Transistors (NCFET).