Demo Data from VLDB 2026 / reviewers in the wild / expert
Akash Gaonkar
dblp:251/2033
· DBLP profile ↗
4ranked-venue papers
1as first author
3since 2021 · last 2026
0000-0001-5565-2581ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 1 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Theory of computation · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
1 paper |
Algorithmic game theory and mechanism design · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Algorithmic game theory and mechanism design › zero-sum game
colonel blotto game |
0.6 | 1 | 2022 | The Derby Game: An Ordering-based Colonel Blotto Game · EC 2022 |
Algorithmic game theory and mechanism design › solution concepts in games › equilibrium concepts
nash equilibrium |
0.6 | 1 | 2022 | The Derby Game: An Ordering-based Colonel Blotto Game · EC 2022 |
Algorithmic game theory and mechanism design › solution concepts in games › equilibrium concepts › nash equilibrium
pure nash equilibrium |
0.6 | 1 | 2022 | The Derby Game: An Ordering-based Colonel Blotto Game · EC 2022 |
Algorithmic game theory and mechanism design › resource allocation
resource allocation game |
0.6 | 1 | 2022 | The Derby Game: An Ordering-based Colonel Blotto Game · EC 2022 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | SecIC3: Customizing IC3 for Hardware Security VerificationabstractRecent years have seen significant advances in using formal verification to check hardware security properties. Of particular practical interest are checking confidentiality and integrity of secrets, by checking that there is no information flow between the secrets and observable outputs. A standard method for checking information flow is to translate the corresponding non-interference hyperproperty into a safety property on a self-composition of the design, which has two copies of the design composed together. Although prior efforts have aimed to reduce the size of the self-composed design, there are no state-of-the-art model checkers that exploit their special structure for hardware security verification. In this paper, we propose SecIC3, a hardware model checking algorithm based on IC3 that is customized to exploit this self-composition structure. SecIC3 utilizes this structure in two complementary techniques: symmetric state exploration and adding equivalence predicates. We implement SecIC3 on top of two open-source IC3 implementations and evaluate it on a non-interference checking benchmark consisting of 10 designs. The experiment results show that SecIC3 significantly reduces the time for finding security proofs, with up to 49.3x proof speedup compared to baseline implementations. Qinhan Tan, Akash Gaonkar, Yu-Wei Fan, Aarti Gupta, Sharad Malik |
DATE | 2 |
| 2024 | Application-level Validation of Accelerator Designs Using a Formal Software/Hardware InterfaceabstractIdeally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs on real applications end-to-end remains prohibitively difficult due to the costs of building specialized compiler and simulator support. We propose a new first-in-class, mostly automated methodology termed “3LA” to enable end-to-end testing of prototype accelerator designs on unmodified source applications. A key contribution of 3LA is the use of a formal software/hardware interface that specifies an accelerator’s operations and their semantics. Specifically, we leverage the Instruction-level Abstraction (ILA) formal specification for accelerators that has been successfully used thus far for accelerator implementation verification. We show how the ILA for accelerators serves as a software/hardware interface, similar to the Instruction Set Architecture for processors, that can be used for automated development of compilers and instruction-level simulators. Another key contribution of this work is to show how ILA-based accelerator semantics enables extending recent work on equality saturation to auto-generate basic compiler support for prototype accelerators in a technique we term “flexible matching.” By combining flexible matching with simulators auto-generated from ILA specifications, our approach enables end-to-end evaluation with modest engineering effort. We detail several case studies of 3LA, which uncovered an unknown flaw in a recently published accelerator and facilitated its fix. Bo-Yuan Huang 0001, Steven Lyubomirsky, Yi Li 0085, Mike He, Gus Henry Smith, Thierry Tambe, Akash Gaonkar, Vishal Canumalla, Andrew Cheung, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik |
ACM Trans. Design Autom. Electr. Syst. | 7 |
| 2022 | The Derby Game: An Ordering-based Colonel Blotto GameabstractThe Colonel Blotto game and its variants are a common approach to study competitive allocation of interchangeable resources (e.g., soldiers, money, or votes). We introduce a new variant of Blotto, which we call the Derby game, to study competitive allocation of non-interchangeable resources, such as campaign surrogates in politics or skilled workers in companies, and analyze its Nash equilibria. While Derby games unsurprisingly admit no pure Nash equilibria, our main results surprisingly show that Nash equilibria generically exist where one player plays a pure strategy, and we give necessary and sufficient conditions for such equilibria. Akash Gaonkar, Divya Raghunathan, S. Matthew Weinberg |
EC | 1 |
| 2019 | Sequential programming for replicated data storesabstractWe introduce Carol, a refinement-typed programming language for replicated data stores. The salient feature of Carol is that it allows programming and verifying replicated store operations modularly , without consideration of other operations that might interleave, and sequentially , without requiring reference to or knowledge of the concurrent execution model. This is in stark contrast with existing systems, which require understanding the concurrent interactions of all pairs of operations when developing or verifying them. The key enabling idea is the consistency guard , a two-state predicate relating the locally-viewed store and the hypothetical remote store that an operation’s updates may eventually be applied to, which is used by the Carol programmer to declare their precise consistency requirements. Guards appear to the programmer and refinement typechecker as simple data pre-conditions, enabling sequential reasoning, while appearing to the distributed runtime as consistency control instructions. We implement and evaluate the Carol system in two parts: (1) the algorithm used to statically translate guards into the runtime coordination actions required to enforce them, and (2) the networked-replica runtime which executes arbitrary operations, written in a Haskell DSL, according to the Carol language semantics. Nicholas V. Lewchenko, Arjun Radhakrishna, Akash Gaonkar, Pavol Cerný |
Proc. ACM Program. Lang. | 3 |