Division, square root, and remainder are fundamental operations required by most computer systems. Floating-point and integer operations are commonly performed on separate datapaths. This paper presents the first detailed implementation of a shared recurrence unit that supports floating-point division/square root and integer division/remainder. It supports early termination and shares the normalization shifter needed for integer and subnormal inputs. Synthesis results show that shared double-precision dividers producing at least 4 bits per cycle are 9 - 18% smaller and 3 - 16% faster than separate integer and floating-point units.

Division and square root are fundamental operations required by most computer systems. They are commonly implemented in hardware using radix-4 recurrence, which produces a 2-bit result digit on each step. Unified digit selection logic chooses the next quotient or square root digit based on a residual and divisor or square root approximation. This paper presents the first derivation of digit selection constants for unified radix-4 recurrence division and square root.

Artificial Intelligence applications do millions of square calculations, such as within Gradient Descent or Principle Component Analysis (PCA). Any time measured or observed data is analyzed; the error, residual, or a comparison against a norm, it is evaluated using a square operation. Squarers are special purpose multipliers that can be employed when the operands are identical. Most calculations use slower multipliers, even though squarers calculate faster, use less power, and occupy less area. Multiplication is composed of a series of partial products that are accumulated to result in the multiplied product. Multiplier and squarer propagation delay is assessed using the number of partial products, or more their addition. The calculation of partial products can occur in parallel, thus does not significantly tax the propagation delay, but carries from their addition create computational dependencies. A standard 8-bit multiplier requires 56 partial product additions and previous work has reduced a squarer to 22 partial products sums. This paper reviews the previous technology and illustrates further Boolean optimizations that minimize the number of additions to 15 partial products.