The TRISTAN project aims to expand and industrialize the European RISC-V ecosystem to compete effectively with existing commercial alternatives. This initiative specifically targets the critical challenges in the development of Electronic Design Automation (EDA) tools, essential for RISC-V-based solutions, by leveraging the synergy between the open-source community and industrial solutions. This paper presents an overview of the current landscape of TRISTAN's EDA flow, highlighting specific tools and methodologies that streamline the early design phases of RISC-V-based systems. We explore the unique features of these tools, emphasizing how they complement each other to strengthen the overall design process.

The evolution towards software-defined vehicles and the intense computational demands of artificial intelligence (AI) are driving the automotive industry to adopt heterogeneous, chiplet-based compute architectures. This paradigm shift is propelled by the need for scalable performance across vehicle models, faster innovation cycles, and cost-effective integration of specialized functions. While this approach offers significant design flexibility, it introduces two fundamental challenges: 1) the complex and time-consuming task of evaluating the performance of countless possible chiplet configurations, and 2) the need to efficiently map and optimize AI inference workloads onto diverse hardware accelerators. This paper addresses both issues. We first detail the requirements for a rapid simulation methodology, emphasizing the need for an open, unified application programming interface (API) that allows for interchangeable hardware models from various vendors. We then demonstrate a hardware-aware AI inference optimization toolchain capable of targeting a wide range of accelerators, ensuring workload portability and performance. By combining these methodologies for rapid evaluation and targeted optimization, we establish a critical pathway for realizing the full potential of high-performance chiplet systems in next-generation vehicles.

This paper presents a demonstrator chip for an industrial audio event detection application developed as part of the Scale4Edge project. The project aims at enabling a comprehensive RISC-V based ecosystem to efficiently assemble well-tailored edge devices. The chip is manufactured in Globalfoundries' 22FDX technology and contains a RISC-V CPU with custom Instruction-Set-Architecture Extensions (ISAX) for fast AI and DSP processing, a low power neural network accelerator, and a scalable PLL to fulfill real-time processing requirements. By automated integration of these specialized hardware components, we achieve a speedup of ×2.15 while reducing the power by 27% compared to the unp[ntimized solution.