360° video processing is rapidly gaining popularity in applications such as entertainment, medical visualization, and immersive training. However, compared to conventional video, 360° video requires significantly higher resources, including bandwidth, power, and memory capacity, due to the large volume of panoramic data. Importantly, not all regions of a 360° frame carry equal visual importance. In this work, we propose an adaptive post-decoder memory architecture that dynamically optimizes video data based on the region of interest. The decoded frame is divided into three regions: Field-of-View (FoV), border, and background. While FoV data is preserved without modification, border and background regions are compressed using flexible bit truncation during memory read operations. This approach reduces redundant data storage and memory bandwidth requirements. Experimental results demonstrate approximately 50% frame size reduction while maintaining about 42 dB WS-PSNR, achieving nearly 19.5% read power savings compared to conventional 360° video processing systems.

Neuromorphic computing has emerged as a promising approach for energy-efficient artificial intelligence by emulating the spatiotemporal behavior of biological neural systems. This work presents a homeostatic plasticity-enabled CMOS neuron integrated with an SRAM-based synaptic architecture for event-driven spiking neural network (SNN) applications. The proposed design combines an 8T-SRAM synaptic framework with a mixed-signal leaky integrate-and-fire (LIF) neuron, enabling efficient spike accumulation without relying on power-intensive data converters. A programmable leak mechanism, governed by a digital homeostatic plasticity controller, dynamically adjusts neuron activity to maintain stable firing rates under varying input conditions. The circuits are implemented in TSMC 65 nm LP CMOS technology and evaluated using both circuit- and system-level simulations. Results demonstrate stable adaptive behavior and significant power efficiency improvements. The proposed architecture achieves an average power consumption of 117.5 μW, where the neuron consumes 58.12 μW and the synapse consumes 59.33 μW, providing 74% lower neuron power compared to state-of-the-art designs. Framework for evolutionary artificial general intelligence (FEAGI) based validation further demonstrates effectiveness in adaptive edge-intelligence applications such as cart-pole balancing.

Machine learning based on memristive dot product engine (DPE) suffers from some practical limitations of memristive synapse which requires constraining the resources such as the number of memristive states and current sensing capability at the classification layer. Constraining those resources saves design time, complexity, and resources but impacts the performance of the system. This paper assesses the performance of DPE-based machine learning across different numbers of memristive states and varying the current sensing resolution at the classification layer. The study found that, for small applications, 8 memristive states are sufficient, with minimal impact observed from increasing the number of states with lower current distinguishability. The analysis also finds that the decreasing current sensing resolution negatively impacts the stability of the system by increasing the random behavior.

The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channel attacks. In this work, we aim to develop a hardware-based technique to achieve differential privacy by design. In contrary to the conventional software-based noise generation and injection process, our design realizes local differential privacy (LDP) by harnessing the inherent hardware noise into controlled LDP noise when data is stored in the memory. Specifically, the noise is tamed through a novel memory design and power downscaling technique, which leads to double-faceted gains in privacy and power efficiency. A well-round study that consists of theoretical design and analysis and chip implementation and experiments is presented. The results confirm that the developed technique is differentially private, saves 88.58% system power, speeds up software-based DP mechanisms by more than$10^{6}$times, while only incurring 2.46% chip overhead and 7.81% estimation errors in data recovery.

Short-term plasticity (STP) is a synaptic modification process found in biological synapses that increases the computational power of the neuronal network. To implement plasticity rules, we use a memristor-based synapse due to its inherent plasticity. The synapse is designed to operate in the low resistance state (LRS) region using a current-controlled mechanism to account for the device non-idealities encountered at the high resistance state (HRS). In this work, we implement a mixed-signal STP circuit for this synapse design. The STP circuit uses a digital part to generate pulses to initiate the weight change, and an analog part to update the programming voltage. The STP functionality is verified using a 65nm CMOS process, and the performance metrics are reported. Results show that our circuit achieves a great performance in terms of area and power consumption.

Memristors are a suitable candidate to design synapse circuits and neuromorphic systems. Due to device and voltage variability, operating a memristive device with reliability is a big challenge. To enhance the reliability of memristive synapse, RESET failure needs to be considered. In this work, we are focused on RESET failure modeling with RESET voltage variation. Here, the RESET failure is defined as hard failure of the memristive synapse due to a high RESET voltage being applied. The proposed Verilog-A model is derived based on experimental data collected from 1T1R devices, which are fabricated on 65 nm CMOS process. To enhance the reliability of system-level simulation, this device model will provide better guidelines to the designer. In addition, power consumption for a successful RESET operation is 7.065 μW at 1.5 V, which can RESET the memristor resistance from 5 kΩ to 200 kΩ.

Neuromorphic computing systems have emerged as powerful computation tools in the field of object recognition and control systems. However, training these systems, which are usually characterized by recurrent connectivity, requires abundant computational resources: memory, computation, data, and time. Reservoir computing (RC) framework reduces this high computational training cost by focusing the training effort on only a small subset of connections thus allowing these systems to be amenable to hardware implementation. Using memristors to construct these reservoir computers reduce the area/power consumption even further. However, the inherent variability of memristors poses specific challenges. Here, we conduct an in-depth reliability analysis of challenges posed by HfO2 memristors, including cycle-to-cycle variability, read/write noise, and conductance drift in the context of RC hardware. We also explore plasticity mechanisms such as Spike-Timing Dependent Plasticity (STDP) within the scope of the spiking recurrent neural networks (SRNN) reservoir and their impact on memristor conductance drift (MCD). We present a chaotic time series prediction task applied to a Python model of the constrained hardware design achieving very low Normalized Root Mean Square Error (NRMSE) of 2 × 10-3. The analog neuron and memristive synapse circuits employed for constructing the SRNN are simulated in Cadence Spectre and the energy consumption for the Mackey-Glass (MG) time-series prediction task was found to be approximately 90 nJ.

Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable in the commonly used voltage-pulse-based programming approaches and require precisely shaped pulses to avoid programming failure. In this paper, we demonstrate a current-limiting-based solution that provides a more predictable analog memory behavior when reading and writing memristive synapses. With our proposed design READ current can be optimized by ~19x compared to the 1T1R design. Moreover, our proposed design saves ~9x energy compared to the 1T1R design. Our 3T1R design also shows promising write operation which is less affected by the process variation in MOSFETs and the inherent stochastic behavior of memristors. Memristors used for testing are hafnium oxide based and were fabricated in a 65 nm hybrid CMOS-memristor process. The proposed design also shows linear characteristics between the voltage applied and the resulting resistance for the writing operation. The simulation and measured data show similar patterns with respect to voltage pulse based programming and current compliance based programming. We further observed the impact of this behavior on neuromorphic-specific applications such as a spiking neural network.

Neuromorphic computing is a leading option for non von-Neumann computing architectures. With it, neural networks are developed that derive architectural inspiration from how the brain operates with neurons, synapses, and spikes. These networks are often implemented in either software or hardware based neuroprocessors designed to handle specific tasks efficiently. Even if implemented in hardware, software emulation is instrumental in determining the worthwhile features and capabilities of the architecture. In this work two novel neuroprocessors are introduced: the software-based RISP neuroprocessor, and the RAVENS hardware neuroprocessor. Several benchmark tests using control applications are performed with each neuroprocessor configured in various ways to evaluate their comparative performance and training properties.

Energy efficiency is nowadays a well-known principal design goal across all layers of computing systems (e.g., sensors, mobile, cloud). With diminishing benefits from CMOS technology scaling and increasing demands from unprecedented data size, new memory hardware innovation is greatly needed to enhance energy efficiency of computing systems. Recently, quality-aware hardware design techniques have been developed from different stack layers (device/circuit/architecture/system) to enable near-threshold/sub-threshold voltage operation by trading off between quality and power efficiency. Specifically, based on the energy-quality trade-off and application requirement, memory hardware is designed for the work mode with maximum quality first (step1-design for the work mode) and then the supply voltage will be adjusted in the sleep mode with just-enough quality to achieve maximum efficiency (step2-adjust in the sleep mode). We first propose mathematical models for this two-step design method to avoid time-consuming and laborious ASIC design iterations in traditional hardware design process. However, such a two-step design method focuses more at the application quality than the energy efficiency in all cases. In addition, as the supply voltage in the second step depends on the design from the first step, the solution space of the second step may be greatly limited, far from the true minimum supply voltage. To handle these issues, we propose a new design concept, the simultaneous quality and energy-sensitive optimal design (SQEOD), in which the two objectives are considered simultaneously rather than by two separate steps. By introducing a system-wised importance weight parameter in the modeling process, our method demonstrates system-specific SQEOD mathematical models for different memory designs with various requirements on the application quality and/or energy efficiency. The results of the numerical studies on embedded memory design show that the proposed models provide a useful and fast tool to enable the optimal hardware designs.

In this article, a flexible power-efficient video memory is presented that can dynamically adjust the strength of error correction code (ECC), thereby enabling power-quality tradeoff based on application requirements. Specifically, we utilize the bit significance characteristics of video data to develop a low-cost parity storage scheme that supports both hamming code-74 (ECC74) and hamming code-1511 (ECC1511). Based on this, we propose a flexible memory with three dynamic power-quality adaptation schemes (i.e., ECC74, ECC1511, and no ECC) to meet different video application requirements. Our simulation results in 45-nm CMOS technology show that the proposed memory can enable up to 35.37% power savings without a noticeable degradation in video quality, as compared to the conventional design. We also design an integrated ECC encoder/decoder that handles both ECC74 and ECC1511, which reduces area overhead. To evaluate the effectiveness of the proposed technique, we further develop a system-level video storage embedded test platform based on a commercial 65-nm SRAM chip, which shows that the proposed technique results in significant supply voltage reduction without noticeable video quality degradation.

The big video data size today imposes huge pressure on storage. The variation and aging induced memory failures significantly influence the video output quality. Recently, researchers have developed different memory designs for videos, deep learning, and other data-intensive applications, which enables better energy-quality tradeoffs with design constraints. Unfortunately, designing memory has been proven to be a very challenging problem due to: 1) various design constraints; 2) multiple memory bitcell design options; and 3) challenging layout integration and cost analysis using different memory technologies. In this paper, we develop novel mathematical models for optimizing embedded video memory design without applying a time-consuming and laborious ASIC design process. The problems are formulated as nonlinear programs and integer linear programs. Different SRAM designs and hybrid SRAM and DRAM designs are considered in our models. The results of the numerical studies show that by applying our proposed method the average mean square error of the video storage can be greatly reduced, even by more than 90% in many cases.

With the advent of Internet of Things (IoT) technologies and availability of a large amount of data, deep learning has been applied in a variety of artificial intelligence (AI) applications. However, sharing personal data using IoT edge devices carries inherent risks to individual privacy. Meanwhile, the energy and memory resources needed during the inference process become a constraint to the resource-limited IoT edge devices. This article brings memory hardware optimization to meet the tight power budget in IoT edge devices by considering the privacy, accuracy, and power efficiency tradeoff in differentially efficient deep learning systems. Based on a detailed analysis on these characteristics, an integer linear programs (ILP) model is developed to minimize mean square error (MSE), thereby enabling optimal input data memory design. Our simulation results in 45-nm CMOS technology show that the proposed technique can enable near-threshold energy-efficient memory operation for different privacy requirements, with less than 1% degradation in classification accuracy.