This article presents hardware-efficient harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation, targeted for the dynamic characteristic testing of high-resolution 14-bit and 16-bit 1 MS/s analog-to-digital converters (ADCs) in VLSI testing environments. For 14-bit ADC testing, a single 16-bit digital-to-analog converter (DAC) with a simplified DPD circuit is demonstrated to achieve a second-order harmonic distortion (HD2) level of −92dBc. For 16-bit ADC testing, where higher resolution is required, we propose a novel dual-DAC architecture utilizing a dual-range synthesis method to enhance effective resolution and suppress harmonics up to the fifth-order (HD2–HD5). Furthermore, to minimize the hardware overhead in practical implementations, we introduce optimized field-programmable gate array (FPGA) design strategies, including time-division multiplexing (TDM) and compressed sine look-up tables (LUTs), achieving a 96.8% reduction in memory usage. The parameters are extracted via a single-step, deterministic calibration flow, ensuring high testing throughput without iterative optimization. Experimental results show HD2–HD5 levels down to −120 dBc, providing a hardware-efficient solution for high-precision built-out self-test (BOST) and future system-on-chip (SoC) integration.

This paper presents a physically unclonable function (PUF) using flash time-to-digital converter (TDC) with linearity self-calibration. The proposed PUF utilizes that the variation of delay of delay elements of TDC is unique to the device and unclonable. The proposed PUF is constructed using the flash TDC with linearity self-calibration using histogram method. With the linearity self-calibration operation, variation of delay elements is estimated. The response output of the PUF is calculated using the estimated variation and the challenge inputs. The proposed PUF is a simple digital circuit consisting of basic digital elements. It is easy to design and implement to both SoC and FPGA. It can be used as not only strong PUF but also as a TDC with fine linearity. The experimental results with Artix7 FPGA show that the intra-chip variation is 8.9 % and the inter-chip variation is 46.9 %. The probability of the correct identification is 99.8 %. Extra resources to construct the proposed PUF are 33.7 % of the resources of the TDC with linearity self-calibration.

This paper describes two harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation with direct digital synthesizer; it is targeted for the dynamic characteristic testing of 14-bit and 16-bit 1MS/s ADCs and their testing sinusoidal wave frequencies are around 100kHz. (i) The first one is an analog-intensive DPD method for the 16-bit ADC testing. The HD2 and HD3 of the original sinusoidal signal are measured with FFT method, and then their 180-degree phase-shifted signals are generated with an auxiliary DAC and added to the original signal to cancel the HD2 and HD3. Our experiments show that −120dBc of HD2 and HD3 can be achieved. (ii) The second one is a digital-intensive DPD method for the 14-bit ADC testing. The digital data of the 180-degree phase-shifted signals of the measured HD2 and HD3 are added to the original digital data of the direct digital synthesizer. The circuit is simple, and our experiments show that −92dBc of HD2 can be achieved. Their details of analysis, simulation and experimental results are shown.

This paper demonstrates that a 20-bit subrange ADC for high precision voltage measurement can be implemented with standard ATE resource and BOST circuits, without special devices. Our prototype 20-bit ADC employs subranging architecture and consists of a 16bit ADC (LTC1867), a 20-bit DAC (ADC5791), Arduino and some additional circuits. Its operation has been confirmed with simulations and experiments, and effects of non-idealities for each circuit to the overall 20-bit ADC performance have been evaluated. We consider that a 16bit audio-band digitizer in an ATE system can be used as the 16bit ADC while the 20-bit DAC as well as an error amplifier (another component for the subranging ADC) can be implemented with BOST circuits.

Testing of analog circuits plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It is a technological challenge including circuit design, signal processing algorithms and measurement methods. This session consists of three talks from industry and academia in this area.

This paper describes the application of our previously proposed residue sampling circuit to RF/Analog Mixed-Signal (AMS) device testing. The residue sampling circuit provides high-frequency signal estimation using multiple low-frequency sampling circuits following an analog Hilbert filter and ADCs; the sampling frequencies are relatively prime. It is based on aliasing phenomena in the frequency domain for waveform sampling and the residue number theory. A high frequency cosine wave is provided as an input signal. Cosine and sine signals with the same frequency are generated by an analog Hilbert filter and are fed into sampling circuits with different (relatively prime) low sampling frequencies. Their analog outputs are analog-to-digital converted and complex FFT is performed on both. Since the high frequency signal is sampled with low frequency clocks, aliasing (spectrum folding) occurs. However, each aliased frequency is different because each sampling clock frequency is different in the sampling circuits. Based on the Chinese remainder theorem, this difference allows the input frequency to be estimated. High frequency resolution can be achieved over long time periods and large numbers of FFT points. We consider here applications to RF/AMS device testing; (i) two tone testing for high frequency narrow band devices, (ii) wireless communication device testing such as LTE, Bluetooth and (iii) wideband analog filter frequency characteristics testing. These considerations are supported by simulations.

Background: In IoT system devices, currents become smaller and they have to operate for ten years with a coin cell battery. Then their accurate and fast measurement is required at the mass production shipping stage. However, the conventional method needs a large resistor (Rm, MΩ-order in Fig. 1) which makes the testing slow, and the ATE environment is noisy.Research Target: Our target is the development of a testing technique to measure the current in the order of nano or sub-nano ampere with high linearity in the noisy ATE environment and in short time as well as with only additional low cost built-out self-test (BOST) circuits.Approach: Fig. 2 shows the proposed current measurement circuits. The current under test is converted to the voltage through an op-amp and a resistor Rmof 10kΩ, and it is then converted to the AC voltage; these conversions are done with small BOST circuits. The AC voltage is amplified and converted to the digital signal through an AC amp, a sample/hold circuit and an ADC. FFT is performed and its power spectrum is calculated; the input current value is obtained. The resistor (Rm) of 10k generates spike noises which are spurious components in the power spectrum. However, usage of the sample/hold circuit reduces their effects. Thanks to the DC-AC conversion, the measurement accuracy is not degraded by the system noise in the low frequency region. The nano-ampere current and the resistor of 10kΩ produces several tens μV level voltage and our previous research in [1, 2] shows that the DC-AC conversion method can measure this level of the voltage accurately and in short time. Also, its multi-channel measurement is possible.Experiment Verification: Preliminary experiment with the prototype system in Fig. 2 was performed and its measured result is shown in Fig. 3. The measurement circuit gain in Fig. 2 was calibrated with 1.0nA input current (Iin), which corresponds to Vin of 10.0μV. Also an offset of 0.2μV due to electromotive force (EMF) was calibrated. We see in Fig. 3 that the proposed method can measure the current as low as 50pA. So far EMF limits the lowest measurable current. Fig. 4 shows 100 times of measurements for 1.0nA without averaging. Each measured current value is obtained by 1K-point FFT with 25.6 ksps, 16-bit ADC (myDAQ) usage and the measurement time of 40ms. The measured data is within 0.94nA to 1.07nA; the variation range is 0.13nAp−p.Conclusion: A method of fast and accurate current measurement as low as 50pA using IV conversion and DC-AC conversion in ATE environment has been developed.

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable; when the repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with the equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing.

This paper demonstrates the harmonic distortion measurement of operational amplifiers by applying our proposed summing node method; we show that it can provide low-cost and high-accuracy testing at the mass production shipping stage. Experiments show that measurement accuracy below -130 dBc is possible without expensive test equipment such as an audio analyzer. We show by theory, simulations, and experiments that the summing node method makes the measurement accuracy robust to the harmonics of the signal source providing the sinusoidal input signal to the operational amplifier under test. In other words, a high precision signal generator is not required. Furthermore, we propose the false summing node method, which does not require direct probing of the summing node, in order to avoid oscillation and instability of the video-band operational amplifier under test. Simulations and experiments verify that it can achieve accurate testing without probing of the summing node and it is robust against the ratio variation of the two resistors in the false summing node testing circuit.

This paper describes that the mature ADC testing method with a simple test system using the incoherent sampling and the standard algorithm of windowing and FFT with 4Kpoint data can measure the SINAD of our target 12-bit SAR ADC accurately by proper setting of the input and sampling frequencies, which is industry-friendly. We show the input sinusoidal signal and sampling clock frequency relationship for accurate testing of the ADC dynamic characteristics with an incoherent sampling method using a flat-top window. We have clarified the measured SINAD accuracy of the input signal frequency dependency for a fixed sampling frequency, a specified resolution of the ADC under test and a given number of FFT points (data samples) in the incoherent sampling environment. Mature technology combinations with their optimal usage and without advanced methods can lead to the low-cost high-quality testing of the ADC, which can be well accepted in industry. Their analysis, simulation and experimental results are shown.

This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.

This paper describes an accurate and fast testing technique for small DC offset voltage of a high precision operational amplifier. Chopper techniques for DC-AC conversion and FFT spectrum analysis are combined and then accurate DC voltage measurement on the order of μV can be achieved. We have also investigated thermo-electromotive force effects and their countermeasures. Their simulations and experiments with prototype measurement systems have been carried out, and the measurement linearity up to as low as 0.2 μV of the DC measurement voltage was confirmed. We have also investigated its extension to multi-channel realization for short testing time.