Grigor Tshagharyan

VLDB 2026 Research / reviewers in the wild / expert

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19ranked-venue papers

2as first author

12since 2021 · last 2025

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 19 · 2 first-author · 12 since 2021Software engineering, systems software and programming languages · 1

Year	Publication	Venue	Position
2025	European Test Symposium Teams: an Anniversary Snapshot abstract The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand	ETS	55
2025	Analysis and Mitigation of Radiation Effects in SRAM-based Register Files Surendra Hemaram, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi Baradaran Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ETS	8
2025	Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack abstract The exponential growth in test data volume for modern Systems-on-Chip (SoCs), combined with a decreasing number of available test pins, has led to increased test time and complexity. Simultaneously, the industry’s drive for higher quality and lower Defective Parts Per Million (DPPM) necessitates continuous monitoring, testing, and repair Silicon Lifecycle Management (SLM). The advent of multi-die packaging technologies, such as 2.5D and 3D stacked integration, further exacerbates these challenges by introducing additional layers of interconnect and access constraints.Universal Chiplet Interconnect Express (UCIe) emerges as a compelling solution for delivering test content to all constituent dies at-speed, post-packaging. UCIe enables seamless test access across various lifecycle stages, including wafer sort, package test, System Level Test (SLT), and In-System Test (IST).This paper introduces a silicon-proven methodology that integrates the UCIe protocol with advanced SLM techniques to address the critical challenges of access, test, measurement and repair in complex multi-die SoC designs. Silicon results from test vehicles fabricated on TSMC N3P process with CoWoS-S packaging demonstrate complete interconnect, logic, and memory test, repair, and monitoring capabilities, validating the effectiveness and scalability of the proposed approach for next- - generation multi-die systems. Sandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee 0004, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan	ITC	16
2024	Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects abstract The long-term reliability of Static Random Access Memory (SRAM) is crucial for safety-critical applications, such as those in the automotive industry. In the front-end-of-line (FEoL), the transistor elements are susceptible to negative bias temperature instability (NBTI), while in the back-end-of-line (BEoL) the interconnects are susceptible to electromigration (EM), especially in scaled technology nodes. To meet safety-critical standards, it is essential to investigate the combined aging mechanisms within the SRAM array and to develop effective testing methodologies during the operational lifetime of the system. Such methodologies are also crucial for enabling the early detection of in-field failures. In this paper, a precise aging model is presented that extends the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model and includes physical modeling for EM. This approach provides insights into the combined effects of NBTI and EM on the degradation of SRAM writability, considering the entire SRAM subarray, including the bit-cell array and peripheral circuits in Fin Field-Effect Transistors (FinFET) technology. Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi Baradaran Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	7
2024	Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management abstract The long-term reliability of the Static Random Access Memory (SRAM) module, as an important component of computing architectures, is crucial for safety-critical applications such as automotive. In the front end of the line (FEoL), the transistor elements are vulnerable to negative bias temperature instability (NBTI), while the back end of the line (BEoL) interconnect is prone to electromigration (EM). Complying with safety-critical standards as part of silicon lifecycle management (SLM) infrastructure requires an understanding of the combined aging mechanisms of transistors and interconnects in SRAM. Moreover, a precise aging model is a prerequisite for effective aging testing and mitigation strategies. For this aim, we augment the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model at the FEoL, and use measurement-calibrated physical modeling of EM at the BEoL, to create an integrated analysis that can provide deeper insights into the individual and combined effects of NBTI and EM for SRAM operation. Our findings reveal the mutual acceleration of delay faults and hard stuck-at faults caused by NBTI and EM in SRAM, offering a precise methodology for estimating the time to failure under these conditions. Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi Baradaran Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	VTS	7
2023	On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI abstract The advanced CMOS technology with smaller feature sizes has greatly improved the performance, energy, and area efficiency of the VLSI systems. Alongside the transistor feature size, back-end-of-the-line (BEoL) interconnects are also shrinking which makes them susceptible to electromigration (EM). Current density and temperature have decisive impacts on the EM profile of the BEoL interconnects, which themselves are highly affected by the running workload. Hence, the actual degradation and the remaining lifetime of a VLSI system are impacted by its usage scenarios. Therefore, in-field monitoring of the chip usage can predict failures before they happen and cause catastrophic failures, and in addition, provide an accurate estimate of the remaining useful lifetime to schedule preventive maintenance. In this work, we propose a simple yet effective on-chip EM sensor that can be embedded as a part of chip silicon lifecycle management (SLM) infrastructure. Further, we show how our proposed EM sensor can be effectively leveraged as a general sensor for the estimation of the remaining useful lifetime of the chip. The simulation results for the 5nm realistic SRAM design show that the power overhead of the proposed sensor is only 0.00365% of the SRAM module with a negligible area overhead. Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ETS	3
2023	Utilizing ECC Analytics to Improve Memory Lifecycle Management abstract With reliability being a critical factor in many applications today, in-system failure detection and correction is a key requirement for ensuring smooth operation in the field. For memory components that occupy the majority of the chip space, this is commonly accomplished with the help of error correcting codes (ECC). However, ECC can offer much more than plain error detection and correction. In particular, the paper describes some of the most common use cases of ECC that help not only to monitor memory health but also to extend its service lifetime by analyzing ECC data over time. Costas Argyrides, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	2
2023	SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor abstract As the size and complexity of System-on-Chip (SoC) continue to grow, product performance and durability requirements have also become a vital part of chip design. By deploying monitors and structures built into the silicon design, we can obtain real-time data on the performance of the chip, which in turn can be used to study the health of the silicon and predict its degradation. This is a particularly important requirement for safety-critical applications such as automotive. In this paper, a case study of Path Margin Monitor (PMM) is presented as part of an automotive SoC subsystem that can monitor the functional paths of silicon in real-time throughout the entire silicon lifecycle. Kranthi Kandula, Ramalingam Kolisetti, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	3
2023	Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era abstract The paper discusses the challenges that memory testing faces in the era of Gate-All-Around transistor technology and proposes a solution concept to overcome them. With the transition from two-dimensional to three-dimensional transistors, and in particular with the advent of FinFET, many new factors have entered the scene, creating a need for new testing techniques capable of coping with the complexity of novel memory designs. However, the end of the FinFET era and the beginning of a new Gate-All-Around design paradigm means that these methods need to be revisited to ensure they remain effective and in line with the latest transistor technologies that are contenders to replace FinFET. The paper assesses the test challenges associated with the Gate-All-Around technology and proposes a solution concept that sets a vector for a thorough investigation of underlying defects, fault modeling, and the development of efficient test and repair algorithms. Artur Ghukasyan, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	VTS	2
2023	An Efficient External Memory Test Solution: Case Study for HPC Application abstract An increasing amount of data are being stored and processed by data centers every day for various commercial and industrial applications. For such large-scale systems dealing with enormous volumes of data, utilization of Dynamic Random-Access Memories (DRAM), integrated into horizontal or vertical stacks, has been proven to be the ideal solution in terms of area vs performance. At-speed test and repair in these stacks of DRAM memories requires complex solutions given the various lifecycle stages the memories go through. In this paper an efficient Built-In Self-Test (BIST) concept is proposed, focusing on both the in-system and production aspects of the test solution. It is demonstrated for a real-life High-Performance Computing (HPC) application. Keqing Ouyang, Minqiang Peng, Yunnong Zhu, Kang Qi, Grigor Tshagharyan, Gurgen Harutunyan, Isaac Wang	VTS	5
2022	An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories abstract Moving to more advanced CMOS technologies can improve the performance and energy efficiency of the VLSI systems, including the static RAM (SRAM) as one of the most demanding memory elements of the modern computer systems. However, the long-term reliability of the SRAM is also important and needs to be carefully considered. This is particularly of utmost importance in safety critical systems, including automotive, with stringent requirements for in-field testing. In advanced technology nodes, the interconnects are designed in a tighter pitch-size, which result in an increase in the current density. Moreover, due to the higher chip complexity, the operating temperature is typically higher. Both the high current density and high temperature exacerbate the electromigration (EM) phenomenon in interconnects, which eventually leads to resistance increase and timing faults. This negatively influences the long-term reliability of the system. Because of the EM, SRAM-based memory modules may undergo field failure, such as read or write faults. To avoid functional safety violation, early detection and prediction of the EM is crucial. In this work, we propose an optimized EM test methodology which is able to predict the effect of EM up to 9.7 months earlier before it leads to failures in normal functional mode. Mahta Mayahinia, Mehdi Baradaran Tahoori, Gurgen Harutunyan, Grigor Tshagharyan, Karen Amirkhanyan	ITC	4
2022	Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety abstract Safety is established as one of top priorities for Automotive SoCs along with security and reliability. However, testing is also known to play a crucial role since the degree of safety indirectly depends on the quality of test solution employed by SoC. In recent years, numerous studies and a large number of papers have been published on this topic, which seemed to form the necessary concepts and requirements for test solutions to achieve the desired level of functional safety. Among others, they introduced the concepts such as power-on self-test, check the checkers, mission mode test, periodic self-test, and so on. At this point, the question naturally arises whether we are hitting the limit, or we are still halfway there, and there is still room to improve field test and further enhance safety. During this session, we will ask speakers who are renowned experts in the field to share their views on the future of automotive industry and what comes next in terms of functional safety. Minqiang Peng, Youfa Wu, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutunyan, Yervant Zorian	VTS	5
2019	Variation-aware Fault Modeling and Test Generation for STT-MRAM abstract Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) offers high density, non-volatility, scalability, high endurance and CMOS compatibility, making it a promising non-volatile memory (NVM) technology. However, due to the unique magnetic fabrication processes, different bit-cell architecture and periphery circuitry, they are susceptible to different manufacturing defects and faults compared to conventional CMOS-based memories. In this paper, a detailed variation-aware defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults. Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Hayk T. Grigoryan, Grigor Tshagharyan	IOLTS	5
2019	Innovative Practices on In-System Test and Reliability of Memories abstract This innovative practice session includes three presentations which discuss test and reliability issues and solutions for external and embedded memories. At speed test for external memories, memory array diagnosis and interconnect faults detection, as well as the peculiarities of supporting different memory IPs including DRAM and HBM2 are among the topics discussed. As for embedded memories, FIT rate calculation and mitigation methodology is presented which is shown to be critical for automotive SoCs. S. Bandyopadhyay, J. Mekkoth, Marc Hutner, Hayk T. Grigoryan, Samvel K. Shoukourian, Grigor Tshagharyan, Yervant Zorian, Gabriele Boschi, Duccio Lazzarotti, Donato Luongo, Hanna Shaheen, Gurgen Harutunyan	VTS	7
2018	Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM abstract Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative technology for on-chip memories due to several advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Due to the emerging fabrication processes of magnetic layers in the fabrication of STTMRAM devices, they are more susceptible to manufacturing defects and have different failure mechanisms compared to conventional CMOS memories. This mandates specific fault modeling and development of proper test algorithms for high coverage testing of these memories in order to ensure correct functionality in the field. In this paper, a detailed defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults. Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutunyan, Yervant Zorian	ITC	4
2018	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications abstract Automotive has become one of the most prevailing sectors of the modern semiconductor industry. Due to strict requirements for safety, reliability, and security the proposed test & repair solutions for automotive applications undergo a circumstantial verification before exploitation. Traditionally production defects and soft errors occurring in the operation mode were considered to be the main source of failures for System-on-Chips (SoC). Nevertheless, aging-induced faults especially in modern technology nodes also pose certain challenges for SoC lifetime and impact the overall Failure in Time (FIT) rate of the system. Meanwhile keeping hold of low FIT rate is one of the main criteria for reliability. In this paper, a comprehensive study on aging faults is conducted for FinFET memories and an efficient test & repair methodology is proposed that meets the automotive requirements and allows decreasing the FIT rate of the system. Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori	ITC	1
2017	An effective functional safety solution for automotive systems-on-chip abstract A functional safety solution based on multi-purpose built-in self-test and repair infrastructure for automotive SoCs is presented. This solution allows building a hierarchical network and managing it in multiple in-field test and repair modes. Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	1
2015	Impact of parameter variations on FinFET faults abstract The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults. Gurgen Harutunyan, Grigor Tshagharyan, Yervant Zorian	VTS	2
2014	Fault modeling and test algorithm creation strategy for FinFET-based memories abstract FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs. Gurgen Harutunyan, Grigor Tshagharyan, Valery A. Vardanian, Yervant Zorian	VTS	2