The proliferation of Internet of Things (IoT) devices in the era of sixth-generation (6G) wireless communication demands ultra-low power and high-frequency circuit solutions to support sustainable, near-zero energy operation. As IoT devices become more ubiquitous in applications such as smart environments, industrial automation, and wearable electronics, there is a growing need for compact and energy-efficient frequency generators capable of operating in the millimeter-wave spectrum. This study presents the design and analysis of a Digitally Controlled Oscillator (DCO) operating at 45 GHz, conforming to the IEEE 802.11aj standard, and implemented using GlobalFoundries 22-nm fully depleted Silicon-On-Insulator (FD-SOI) technology. The oscillator core adopts a complementary Colpitts topology, chosen for its efficiency and suitability at high frequencies. Frequency tuning is achieved through a digitally controlled switched capacitor array, implemented with lowleakage transmission gates. Operating at a low supply voltage of 0.8 V, the proposed DCO achieves a power consumption of only 5.959 mW and demonstrates excellent spectral purity, with a phase noise of −99.03 dBc/Hz at 1 MHz offset, making it ideal for ultra-low-power mmWave receivers in dense IoT networks.

This paper presents the design and performance evaluation of a low-power, high-frequency Digitally Controlled Oscillator (DCO) incorporating an active inductor, implemented using 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology. Tailored for energy-constrained Internet of Things (IoT) devices-particularly those relying on RF energy harvesting-the proposed DCO achieves a frequency tuning range from 44.78 GHz to 45.35 GHz, while maintaining a total power consumption of less than 12 mW. The integration of an active inductor replaces conventional bulky passive inductors, enabling significant area reduction and improved compatibility with standard CMOS processes. This makes the design highly suitable for compact and scalable on-chip RF systems. Although the design exhibits a moderate phase noise of$-78.96 \text{dBc} / \text{Hz}$at 1 MHz offset, it offers a well-balanced trade-off between power efficiency, frequency performance, and spectral purity. Overall, the proposed DCO architecture demonstrates a viable solution for next-generation, low-power mmWave transceivers in dense IoT networks and other wireless sensor applications.

This study presents a dual-band impedance matching technique designed for wireless power transfer (WPT) applications operating at 900 MHz (UHF/GSM) and 2.45 GHz (Wi-Fi/ISM) frequencies. The proposed method employs a bridged-T coil (BTC) network integrated with a single-stub tuning approach to simultaneously match the input impedance at both frequency bands, ensuring efficient power delivery. Fabricated using 65nm CMOS technology, the rectifier circuit demonstrates promising performance metrics. At an input power of −15dBm, the power conversion efficiency (PCE) reaches 58.01 percent at 900 MHz and 50.52 percent at 2.45 GHz. Under higher input power of −3 dBm, the peak PCE improves to 68.57 and 57.44 percent for 900 MHz and 2.45 GHz, respectively. The design also achieves a dynamic range of 19.04 dB at 2.45 GHz, indicating robust performance across varying input levels. Furthermore, excellent return loss (S11) values are observed, with −34.48 dB and −13.27 dB at 900 MHz, and −11.28 dB and −16.27 dB at 2.45 GHz for GSM and Wi-Fi bands, respectively.

This paper presents a low quiescent current outputcapacitorless low-dropout (LDO) regulator implemented in 65nm CMOS technology dedicated to the power management in Energy Harvesting Unit (EHU) applications. Most of the blocks in the proposed circuit operate in the subthreshold region in order to provide their specific outputs while consuming less current. To further reduce current consumption, a subthreshold voltage reference which can also be used to bias the error amplifier while providing a voltage reference of 500.2 mV with a TC of 55ppm/°C and a power consumption of 433.2 nW is utilized. The proposed LDO regulator uses a current-efficient adaptively biased regulation using two power transistors. The adaptive biasing circuit senses the load current and adjusts the bias point of the amplifier correspondingly. The results from the simulation demonstrate that the low dropout regulator can achieve a remarkably low quiescent current of 1.98859uA and a power consumption of 2.349134 uW under no load conditions. Additionally, the LDO regulator has a PSRR of −50.3228 dB, a good stability margin of 72.66°, and a maximum settling time of 3.437 us all under different load conditions. Moreover, the regulator can successfully maintain a regulated output voltage of 1V from a supply voltage of 1.2V, with a dropout voltage of 200 mV leading to an overall efficiency of 83.33%. Furthermore, the overall chip layout area is 0.0739 mm2.

An inductorless differential Low Noise Amplifier (LNA) with high linearity, designed for geofencing applications, is presented. The LNA incorporates gm-boosting, linearity optimization, and noise-cancelling stages. A complementary derivative superposition technique is used for gm-boosting, while a common-source noise-cancelling path is employed to implement the linearity enhancement stage. The design uses a differential structure for linearity optimization, addressing inherent stability issues associated with the technique. Implemented in 65nm technology, the LNA occupies a chip area of 0.037 mm2and achieves a noise figure (NF) of 3.03 dB, a peak gain of 16.78 dB, and an IIP3 linearity of 9.94 dBm, with a power consumption of 28 mW. The LNA demonstrates good stability and process variation tolerance.

This paper presents a novel approach to voltage reference design, harnessing the bulk biasing technique in 22nm Fully Depleted Silicon-on-Insulator (FDSOI) technology. The proposed architecture exhibits ultra-low power consumption of 95.28 nW while having a dissipating supply current of 157 nA and a high Power Supply Rejection Ratio (PSRR) of more than -100 dB, realized through an all-MOSFET construction where TC compensation of PTAT and CTAT voltage generators is adopted. A temperature coefficient of$22.22\text{ppm}/^{\mathrm{o}}\mathrm{C}$is achieved over wide temperature range from$-45^{0}\mathrm{C}$to$100^{\prime} \mathrm{C}$with an output voltage VREF of 351 mV. With the growing demand for efficient, low-power, and compact solutions in Internet of Things (IoT) power management, this development contributes a significant step forward in the domain.

This paper presents a design of a hybrid multistage differential rectifier dedicated for indoor light energy harvesters. For the first stage, a fully cross- coupled rectifier with two additional PMOS switches is used and conventional fully cross-coupled rectifiers are cascaded for the succeeding six stages. The proposed rectifier is designed using TSMC 65nm CMOS process for a smaller chip area. With an input voltage of 0.5 V operating at 10 MHz, the circuit obtained an output voltage of 2.08 V and output current of 10.4 mA. It allows improving the output current to as much as twice the value compared to that of a conventional multistage differential rectifier structure. The maximum power conversion efficiency obtained is 43.08 %. The total core chip area is 0.052 um2. All the design underwent multiple thorough verifications and simulations using Synopsys Custom Design Tool.

This paper introduces a low-quiescent and reduced-power zero current detector (ZCD) designed specifically for a DC-DC switched-mode converter operating in discontinuous current mode. The ZCD incorporates control switches strategically placed to minimize power consumption and leakage current. The ZCD operation is enabled through a ZCD controller circuit, which efficiently manages the power consumption. The controller circuit generates a voltage to control the ZCD, ensuring that the control switches are triggered only when the inductor current is about to change polarity, typically occurring when the low-side power switch of the converter is active. Once the zero current is detected, the ZCD becomes inactive after a slight delay of 1ns, as defined in this paper. The ZCD controller circuit comprises flip-flops and logic gates, managing the ZCD's activation and deactivation. Control switches are strategically placed at each branch of the ZCD circuit to optimize its efficiency. To monitor the inductor current of the DC-DC converter, the voltage polarity at one end (input side) of the inductor is sensed in relation to the ground. The ZCD is configured with transistors in reverse back gate biasing, further enhancing its performance and efficiency. The simulation results showcase impressive outcomes, with the ZCD exhibiting a quiescent current of 1.13nA and an average current of 323nA at a 0.8V supply voltage. This design is implemented using the advanced 22nm FDSOI technology, showcasing its practicality and relevance in modern circuit design.

This paper introduces a Schmitt trigger with ad-justable hysteresis, specifically developed for low power per-formance and fabricated using 22nm FDSOI technology. The proposed design incorporates a dynamic threshold voltage gen-eration technique to achieve both reduced power consumption and high noise immunity. The voltage-controlled hysteresis is adjustable to enable the design to be customized for different applications. The Schmitt trigger is implemented using a stan-dard CMOS process and the circuit performance is analyzed using Cadence Virtuoso simulation. The outcome presents that the suggested design achieves a low power consumption ranging from nW to pW and a high noise immunity with an adjustable hysteresis of 0 V to 0.4V to both gate voltages. The suggested design is well-suited for low power requirements in various digital circuit applications, including memory, microprocessors, and sensors.