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Timo Zijlstra

dblp:254/8734 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2022
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 44% Integrated circuit design · 44% Electronic design automation · 13%
Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis › post-quantum cryptography
lattice-based cryptography		 0.612022
Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS · IEEE Trans. Computers 2022
Integrated circuit design › digital circuit design
cryptographic hardware		 0.612022
Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS · IEEE Trans. Computers 2022
Reconfigurable computing and FPGAs
FPGA accelerator		 0.612022
Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS · IEEE Trans. Computers 2022
Electronic design automation
high-level synthesis		 0.212022
Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS · IEEE Trans. Computers 2022

Methods — techniques the papers use, named apart from their topics

parallelization · 1.1high-level synthesis · 1.1design space exploration · 1.1
YearPublicationVenuePosition
2022 Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS
abstract
This paper deals with hardware implementations for lattice-based cryptography. Various CPA and CCA secure algorithms for LWE, RLWE and MLWE problems have been studied, parallelized, implemented and compared on FPGA using high-level synthesis. The impact of PRNG choices on the implementations performances and costs is also evaluated. HLS allows us to compare various sets of algorithms, architectures and parameters with a reduced design effort. Our results are often similar to state-of-the-art for various speed and cost trade-offs. Sometimes we obtain better results thanks to the exploration of numerous architecture and algorithm optimizations.
Timo Zijlstra, Karim Bigou, Arnaud Tisserand
 IEEE Trans. Computers1