Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Ardhendu Sarkar

dblp:255/2092 · DBLP profile ↗
← Back
3ranked-venue papers
3as first author
1since 2021 · last 2024
0000-0002-4555-3026ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Bioinformatics and computational biology · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Bioinformatics and computational biology
sequence alignment
0.812024
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware accelerators and domain-specific architectures
bioinformatics accelerator
0.812024
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware accelerators and domain-specific architectures › bioinformatics accelerator
sequence alignment accelerator
0.812024
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

pipelined processing · 1.5parallel trace-back · 1.5
YearPublicationVenuePosition
2024 Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment
abstract
Due to the exponential growth of sequence databases, the processing of genome sequencing in real-time is a fundamental problem. Though several schemes have been developed over the years, unfortunately, they suffer from time-consumption, power-consumption, and resource-bound trade-off issues. Another major issue concerns designing efficient architecture to perform the alignment of multiple sequences. A novel hierarchical multiprocessing architecture, designed around pipelined processing elements, is presented for multiple pair-wise sequence alignment at hardware-speed. In addition to parallel intra-sequence trace-back value generation, it can efficiently perform parallel inter-sequence computation to attain maximum utilization of processing elements. It can accomplish parallel trace-back operations to achieve massive parallelism. It consumes O(ni) or O(ji) clock-cycles to perform alignment operations for j-nucleotide query and i reference sequences of n-nucleotide, instead of O((n+j)i) or O(nji) clock-cycles used in state-of-the-art architectures. The entire architecture is evaluated for 16-to-512 multiple sequences of 16-to-512 nucleotides. It achieves ≈1.6 to ≈24 GCUPS (GCUPS: Giga Cell Updates Per Second) throughput and ≈5 to ≈12.5 GCUPS/W power-efficiency for 16-to-64 sequences and ≈1.6 to ≈5.6 GCUPS/W for 128-to-512 sequences. The peak throughput for 1024-nucleotide sequence is 128 GCUPS, and power-efficiency is 41 GCUPS/W. Finally, the presented architecture exhibits a gain of ≈2× in throughput and ≈6× in power-efficiency compared to state-of-the-art architectures.
Ardhendu Sarkar, Surajeet Ghosh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2020 An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment
abstract
Biological sequence alignment procedure demands an accurate, high speed, and efficient system to align sequences due to exponential growth of genomic databases. Several software-based as well as hardware-based schemes have been developed to perform alignment operation. Unfortunately, these approaches do not meet the requirement of hardware resource and processing time of recent growth of biological sequences. This article presents a pipelined-multiprocessor architecture with an energy-efficient approach to meet the requirement of processing of alignment operation at hardware speed. This architecture introduces register-file concept, instead of conventional memory-based approach, to reduce run-time storage requirement as well as power consumption. In addition, the proposed alignment architecture does not incur any preprocessing operations present in most of the existing alignment approaches. Moreover, it does not need any sorting or comparison operation during the preparation of final sequence alignment. This architecture achieves 128 GCUPS performance and also acquires 107.20 GCUPS/W throughput with respect to power consumption. The proposed architecture brings down 97.29% power consumption compared to state of the art multiprocessor architectures. Experimentally, it has been observed that, this novel architecture exhibits reduction in energy consumption by ≈97.51% and achieves 2.56 GCUPS gain factor in an energy-efficient manner over all existing hardware approaches.
Ardhendu Sarkar, Som Banerjee, Surajeet Ghosh
IEEE Trans. Very Large Scale Integr. Syst.1
2019 Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU
abstract
Sequence alignments are currently gaining close attention due to their great impact on the quality aspects of life such as facilitating early disease diagnosis, identifying the characteristics of a newly discovered sequence, etc.. With the rapid growth of genomic data, searching for a sequence homology over huge databases is unable to produce results within a realistic time. Hence, it demands an efficient sequence alignment accelerator to improve the performance of the system. Though some popular acceleration platforms, like supercomputers, Very Large Scale Integration (VLSI) chip, Graphics Processing Unit (GPUs) and Field Programmable Gate Arrays (FPGAs) based devices are available, but they are unable to meet the intended requirement to the current growth of genome database. This paper presents a parallel dynamic approach for global pairwise alignment algorithm using GPU to handle such large database. The approach performs the alignment procedure in CUDA-enabled GPU platform by creating dynamic threads to perform parallel execution. This GPU-based implementation is tested using pseudorandom database and various length of sequences. The execution result shows reasonably better performance in terms of time and space requirement with respect to existing GPU-based optimal pairwise sequence alignment approaches.
Ardhendu Sarkar, Kinjal Ray, Debaroti Chowdhury, Kishan Sahu, Solanki Kundu, Surajeet Ghosh
TENCON1