Rapid and accurate performance estimation is critical in evaluating novel microarchitectures, as it enables efficient exploration of architectural trade-offs. Unfortunately, traditional simulation techniques, while precise in predicting performance and power, incur tremendous slowdowns versus real machines. Despite prior works having explored machine learning–based performance prediction, the area remains far from sufficiently studied with existing approaches typically requiring large comprehensive datasets, frequent retraining, and heavy memory footprints with limited accuracy. Here, we introduce a new, fast and accurate, early-stage preview framework that uses partial simulation data, and leverages a smaller, faster tree-based machine learning (ML) model to forecast performance metrics such as IPC and Power. By training on a diverse set of configurations, our framework dynamically captures relationships between microarchitectural parameters in large OoO cores versus overall performance and other metrics. Collecting data from as few as 10 sample points taken during warmup, representing only 25 million instructions, our models achieve mean absolute percentage errors of 3-4%, preserving a majority of the model’s predictive accuracy while achieving a 25× speedup (96% reduction in simulation time). By comparison, linear regression techniques from the same point in simulation show an error of 50%. In cache DSE, we improve ranking accuracy by 25× compared to state-of-the-art prediction methods. Our results also show the proposed framework can accurately predict the performance of unseen (untrained) microarchitectural components including new prefetchers and branch predictors.

Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO's), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement.

Continuous monitoring of cardiac health through single-lead wearable Electrocardiogram (ECG), is important for paroxysmal Atrial Fibrillation (AF) detection. Wearable ECG straps, watches, and implantable loop recorders (ILR) are based on this paradigm. These devices are used by medical professionals to view data from multiple patients, perform continuous monitoring and analysis to provide immediate care to patients. These monitoring devices display simple health screening alerts to the subjects and generate distress signals for people working outdoors or in isolated environments with intermittent Internet connectivity. Hence, low-memory, low-power, low-latency on-device inference becomes very important. This work aims at realizing such solutions by providing a framework to generate tiny (less than 256 KB) Deep Neural Networks customized for typical microcontrollers (MCU) used in those devices.

A systolic array implementation of image segmentation by a split and merge procedure is proposed. The implementation enhances the input/output and memory bandwidth requirements, leading to a decrease in the computation time for the segmentation of an image. Image segmentation through the proposed approach can be achieved in linear time.>