While learning personalization offers great potential for learners, modern practices in higher education require a deeper consideration of domain models and learning contexts, to develop effective personalization algorithms. This paper introduces an innovative approach to higher education curriculum modelling that utilizes large language models (LLMs) for knowledge graph (KG) completion, with the goal of creating personalized learning-path recommendations. Our research focuses on modelling university subjects and linking their topics to corresponding domain models, enabling the integration of learning modules from different faculties and institutions in the student's learning path. Central to our approach is a collaborative process, where LLMs assist human experts in extracting high-quality, fine-grained topics from lecture materials. We develop a domain, curriculum, and user models for university modules and stakeholders. We implement this model to create the KG from two study modules: Embedded Systems and Development of Embedded Systems Using FPGA. The resulting KG structures the curriculum and links it to the domain models. We evaluate our approach through qualitative expert feedback and quantitative graph quality metrics. Domain experts validated the relevance and accuracy of the model, while the graph quality metrics measured the structural properties of our KG. Our results show that the LLM-assisted graph completion approach enhances the ability to connect related courses across disciplines to personalize the learning experience. Expert feedback also showed high acceptance of the proposed collaborative approach for concept extraction and classification.

Field-Programmable Gate Arrays (FPGAs) have received significant attention in academic and industrial research due to their reconfigurability, power efficiency, and ability for real-time high-performance computation. The growing demand for FPGA-based systems across various applications has necessitated the development of robust design and verification platforms to support academic and research objectives. In pursuit of this long-term goal, numerous FPGA-based remote laboratory platforms have been proposed, emphasizing didactic needs. However, more attention must be paid to requirement analysis and evaluation criteria specific to FPGA-based remote laboratory platforms. This paper addresses this gap by investigating state-of-the-art remote laboratory platforms alongside a comprehensive requirement analysis. A didactic evaluation has been conducted to assess qualitative and quantitative data to effectively align requirements with outcomes, providing insights into students' perceptions of the platform and its efficacy in meeting learning objectives. Furthermore, the evaluation highlights students' engagement with laboratory tasks across different time intervals throughout the day. However, this requirement analysis and evaluation serve as a foundation for effectively designing an efficient FPGA design and verification platform, fostering enhanced learning experiences in remote laboratory settings.

The integration of renewable energy and hydrogen-based systems into smart grids requires a robust and determonistic communication infrastructure. This study presents a Time-Sensitive Network (TSN)-based smart grid architecture to facilitate secure and real-time data exchange between decentralized energy producers, storage units, and consumers. The proposed framework incorporates key TSN mechanisms, including IEEE 802.1AS (time synchronization), IEEE 802.1Qbv (traffic shaping), and IEEE 802.1CB (fault tolerance), to ensure reliable operation in dynamic energy environments. This work evaluates the feasibility of the proposed architecture through theoretical analysis and system modeling as an initial step. Key challenges such as network resilience, compliance with IEC 61508, and interoperability with existing industrial energy infrastructures are examined. Future research will focus on practical validation through fault injection experiments and Hardware-in-the-Loop (HIL) testing. The results contribute to developing a scalable and standardized TSN-based smart grid architecture that supports the transition to hydrogen-powered industrial energy systems.

This work-in-progress paper presents the current development of a new collaborative remote laboratory platform. The results are intended to serve as a foundation for future research on collaborative work in remote laboratories. Our platform, standing out with its adaptive and collaborative capabilities, integrates a distributed web-application for streamlined management and engagement in diverse remote educational environments.

The subsequent structural health monitoring plays an essential role in system health management applications for buildings, power plants, aircraft, and railways. This paper designs and evaluates a high-precision signal generator based on field programmable gate arrays (FPGA) for guided waves to be used in ultrasonic systems for the structural health monitoring (SHM) domain. A system model of the signal generator is designed by StarUML and implemented in Xilinx Vivado. The design and implementation are based on the Zynq 7010 system-on-Chip (SoC) integrated on the evaluation board RedPitaya. However, the designed architecture is represented in detail, showing the functionality of the implemented VHDL hardware modules. For better evaluation, generated signal by RedPitaya with the calculated signal in MATLAB and generated signal on the Handyscope HS6 are compared. Through theoretical analysis and experimental verification, the test results demonstrate that the FPGA-based signal generator can generate the required excitation signal for ultrasonic guided wave and this signal can accomplish the system’s purposes.

As the level of System-on-Chip (SoC) based embedded systems complexity continues to enlarge, the post-silicon validation stage contributes a major part of the entire development cost. Due to precipitous design complexity, it is nearly unattainable to detect and fix all design errors during the design phase. This paper presents a solution to resolve this problem with the help of a novel In-Circuit Debugger (ICD), which aims to enhance the post-production validation process by enabling observation and control of internal signals, such as input and output signals of safety critical systems. The ICD is an efficient technique for monitoring and verification of on-chip IP-cores. This paper proposes a novel system debugging technique and explains how it differs from existing techniques. Moreover, various use cases of ICD are also discussed in detail.

In domains such as aerospace, wind turbines and railway, structures are exposed to tough environmental conditions. Structural Health Monitoring (SHM) systems offer the possibility to realize condition-based maintenance (CBM) and monitoring methods in order to prevent fatal accidents. For this reason, real-time processing of the acquired data is necessary. The real-time processing of this data in combination with safety requirements and high availability needs a safe platform that can provide high computational power. In this paper a System-on-Chip (SoC) platform is shown, which addresses these challenges through the combination of an ARM processor with Programmable Logic (PL). Based on the SoC, the integration of safety-critical and non safety-critical functionality is possible in a single device. Targeting the standards EN 61508, EN 50126 and EN 50657 the introduction of SoCs as a platform for certifiable systems is discussed. With diversity and redundancy on a single chip, SoCs are ideally suited for requirements such as reliability, availability, maintainability and safety. Moreover, the implementation of functions in hardware on the PL in connection with the Programmable System (PS) facilitates real time data processing.