Ferroelectric FET (FeFET)-based arrays are promising candidates for energy-efficient, high-density non-volatile memory in data-intensive applications. However, charge-trappinginduced degradation and process variations pose significant reliability challenges. These effects lead to reduced memory window and degraded read accuracy over time. We propose a workload-aware degradation modeling and readout framework for FeFET arrays. First, we select a small set of representative workloads to efficiently capture degradation trends across a large workload space. We apply a two-step method to reduce read error: (a) adjust intermediate state currents to widen the separation between states; (b) select optimum reference thresholds based on the shifted distributions. Next, we perform detailed tradeoff analysis involving degradation improvement, on-chip area, and the overhead of a memory-mapped CPU polling system for in-field workload tracking. This is the first work to propose adaptive reference prediction for FeFETs based on runtime workload characteristics. Our framework improves read reliability with minimum hardware overhead and enables scalable in-field monitoring for future FeFET-based systems.

Ferroelectric field-effect transistors (FeFETs) have many promising applications, but the impact of manufacturing imperfections on these devices has yet to be studied comprehensively. We extend a previous FeFET compact model to combine the Preisach ferroelectric capacitor model with the BSIM-SOI MOSFET model. We calibrate this new compact model with data from a technology CAD model that is calibrated against a fabricated metal-ferroelectric-metal capacitor. We analyze polarization defects in the ferroelectric layer using this compact model. We address two classes of defects and map them to stuck-at-fault models, referred to as neutral faults, and stuck-at-plus and stuck-at-minus faults. We also present an analysis of the impact of device-level opens, shorts, coupling faults and extrinsic variations on the multi-level FeFET device in a 1T-1FeFET cell. Simulation results under a clustered fault distribution with a 2% fault rate for faults show a maximum accuracy degradation of 83.86% and 81.66% for ResNet18 and VGG16, respectively when inferencing is performed on faulty FeFET crossbar designs. Similarly, extrinsic variations and clustered polarization defects show a maximum accuracy degradation of 80% and 75% across both DNN models, respectively. We also evaluate the effectiveness of write-verify for mitigating the impact of extrinsic variations, polarization defects, and BEOL faults.

Warpage is a major concern in fan-out wafer-level packaging (FOWLP) due to the complex thermal processing steps involved in manufacturing. These steps include curing, electroplating, and deposition, which induce residual stresses through differential thermal expansion and contraction of materials. This effect is further amplified by mismatches in the coefficients of thermal expansion (CTE) between different materials. In particular, high-density interconnects in the back-end of line (BEOL), redistribution layers (RDLs), and through-mold vias (TMVs) are susceptible to warpage-induced stress, strain, and deformation. This work conducts structural simulations to analyze warpage in the BEOL stack induced by FOWLP. Our results indicate that the impact of warpage is non-uniform across the entire BEOL geometry of a die, hence it impacts different metal layers differently, and different coordinates within one metal layer differently. We leverage this warpage analysis to calculate parasitics and evaluate the resulting changes in path delays.

Fan-out wafer-level packaging enables heterogeneous chiplet integration via Cu pillars and redistribution layers (RDLs). As FOWLP technology evolves, the focus is shifting towards many-chiplet designs, necessitating multi-layer RDL structures to route interconnects between these chiplets. However, defects such as opens, shorts, and coupling are a challenge for RDL structures. High-density, multi-layer RDLs exacerbate these challenges, leading to intensified coupling, elevated switching activity, and shorts within metal segments. Moreover, the finer pitch of RDLs increases electromigration due to rising current densities. We propose a routing-aware testing framework that leverages the multi-layer RDL routing Information to target realistic shorts and coupling defects. By physically partitioning interconnects into regions, we enable test scheduling and leverage shared test-pattern generators for launching test patterns and capturing responses to reduce test time and area overhead without compromising fault coverage. The framework’s effectiveness is demonstrated on four many-chiplet package designs with varying configurations of chiplet-to-chiplet connectivity. Our results show that this method can achieve over 99.8 % fault coverage with an n-fold reduction in test area and test time through an n-way partitioning strategy.

Safety-critical applications such as autonomous driving demand rigorous functional safety assurance. We present a safety-guided test pattern generation framework called NeuralTPG for transition faults in integrated circuits (ICs) based on Launch-on-Capture (LOC) delay testing. We model the logical state transition behavior of standard cells using multilayer perceptrons (MLPs), referred to as Cell-Nets. The neural twin is constructed by converting standard cell instances into Cell-Nets and replacing inter-cell wires with neural connections. We leverage the end-to-end differentiability of the neural twin to compute input test-pattern pairs for transition faults through back-propagation. The neural twin enhances fault propagation to primary outputs (POs) and generates test-pattern pairs that maximize faults’ propagation capability. The framework supports non-binary, user-defined criticality-factor (CF) assignment across the circuit’s internal nets and POs, enabling CF-guided test-pattern pair generation to propagate transition faults to more critical POs. NeuralTPG employs concurrent test generation, fully leveraging GPU acceleration to generate test-pattern pairs for all transition faults simultaneously, thereby improving test efficiency. Experimental evaluations on six benchmarks across three CF configurations demonstrate that NeuralTPG can be used to achieve safety-guided fault propagation.

Ferroelectric Field-Effect Transistors (FeFETs) are emerging as promising candidates for non-volatile memory and in-memory computing due to their low power consumption, fast switching speeds, and high integration density. However, device-level defects and process variations pose significant challenges to their reliability, particularly for multi-level cell (MLC) FeFETs. Polarization defects in the ferroelectric layer and back-end-of-line (BEOL) defects lead to memory window reduction and erroneous computations in FeFET-based crossbars. We propose a March test solution tailored for MLC FeFETs that detects and diagnoses BEOL defects in the presence of underlying process variations and polarization defects.

Analog and mixed-signal (A/MS) integrated circuits (ICs) are crucial in modern electronics, playing key roles in signal processing, amplification, sensing, and power management. Many IC companies outsource manufacturing to third-party foundries, creating security risks such as syntactical bugs and stealthy analog Trojans. Traditional Trojan detection methods, including embedding circuit watermarks and hardware-based monitoring, impose significant area and power overheads while failing to effectively identify and localize the Trojans. To overcome these shortcomings, we present SPICED+, a software-based framework designed for syntactical bug pattern identification and the correction of Trojans in A/MS circuits, leveraging large language model (LLM)-enhanced detection. It uses LLM-aided techniques to detect, localize, and iteratively correct analog Trojans in SPICE netlists, without requiring explicit model training, and thus incurs zero area overhead. The framework leverages chain-of-thought reasoning and few-shot learning to guide the LLMs in understanding and applying anomaly detection rules, enabling accurate identification and correction of Trojan-impacted nodes. With the proposed method, we achieve an average Trojan coverage of 93.3%, average Trojan correction rate of 91.2%, and an average false-positive rate of 1.4%.

Many real-life safety-critical applications such as autonomous driving require functional safety. We present a framework for functional safety-guided test pattern generation. We incorporate the functional information of each standard cell into a multi-layer-perceptron (MLP), referred to as Cell-Net. Each Cell-Net is a pre-trained MLP that models the behavior of the corresponding standard cell. The design netlist is translated into its neural twin, where the standard cell instances are substituted by their corresponding Cell-Nets and the wires in the netlist translate to neural connections between these Cell-Nets. We leverage the neural twin-enabled back-propagation for gradient computation, and utilize these gradients to compute test patterns. The output of every Cell-Net is associated with a bias that represents a perturbation in the signal propagating through that Cell-Net. We manipulate these bias values to inject stuck-at faults at the output of Cell-Nets. We utilize the neural twin to enhance the propagation of faults to primary outputs (POs), and find the test patterns that maximize the propagation of faults to POs. The neural twin also enables the assignment of non-binary criticalityfactors (CFs) to different POs and perform a test-pattern search for each fault for a given CF configuration. Our results on five benchmark circuits across three different CF configurations show an increased fault propagation achieved by the neural twin as compared to Automatic Test Pattern Generation (ATPG).

Ferroelectric field-effect transistors (FeFETs) are a promising emerging non-volatile memory, but the impact of manufacturing imperfections on these devices has yet to be studied comprehensively. We extend a previous FeFET compact model to combine the Preisach ferroelectric capacitor model with the BSIM-SOI MOSFET model. We calibrate this new compact model with data from a technology CAD (TCAD) model that is calibrated against a fabricated metal-ferroelectric-metal capacitor. We analyze polarization defects in the ferroelectric layer using this compact model. We address two classes of defects and map them to stuck-at-fault models, referred to as neutral faults (SAP0), and stuck-at-plus and stuck-at-minus (SAP+and SAP−) faults. This framework obviates the need for computationally expensive TCAD simulations for each defect scenario.

Emerging devices are susceptible to manufacturing defects due to immature fabrication processes. Ferroelectric field-effect transistors, referred to as FeFETs, are promising emerging devices, but the impact of manufacturing imperfections on these devices has yet to be studied. Thus, we combine a technology CAD (TCAD) model with a fault-injection technique to represent fabrication defects in a FeFET. The TCAD model is calibrated against a fabricated metal-ferroelectric-metal capacitor and uses a multi-domain ferroelectric-layer structure. We address two classes of defects in the ferroelectric layer and map them to stuck-at-fault models referred to as neutral faults (SAP°) and stuck-at-plus and stuck-at-minus (SAP+and SAP−) faults. We also develop a machine-learning (ML) framework to characterize these fault-injected FeFET devices. The ML framework provides a significant speedup in predicting the health of the FE layer as compared to computationally heavy TCAD simulations. Our study of defects in ferroelectric FET (FeFET), which is done for the first time, and the insights gained thereof can provide valuable feedback for the fabrication and yield learning of FeFET-based circuits.