Multiple threshold voltage (multi-Vth) optimization reduces leakage by replacing low-Vth cells with high-Vth cells but is limited by tight design constraints and timing violations on critical paths. This paper proposes a novel approach using mixed-Vth cells, where pull-up and pull-down networks are independently optimized for different Vth types. By selectively assigning higher Vth to only one of the networks, the proposed method achieves significant leakage reduction without violating timing constraints. The methodology ensures to satisfy the constraint of minimum implant width through localized cell relocation. Experimental results show a reduction in leakage power by 22% on average with no timing violation in practical runtime, while the conventional cell-based method reduces 10% of leakage.

IR-drop analysis of analog circuits is a challenge because the current waveforms of target transistors, with connection to VDD or VSS, are extracted through transistor-level simulation, and the analysis itself, in particular dynamic one, is computationally expensive. We introduce two ML models for high-speed analysis. (1) Recurrent synchronized graph convolutional network (RS-GCN) is used for quick prediction of current waveforms. Each subcircuit is modeled with recurrent-GCN, in which recurrent connection is for the analysis in discrete time series. Recurrent-GCNs are synchronized to take account of common connections including VDD, VSS, and the inputs and outputs of subcircuits. Experiments show that RS-GCN takes only 0.85% of SPICE runtime, while prediction error is 14% on average. (2) Y-Net is applied for actual IR-drop analysis of small layout partition, one by one. Pad location and PDN resistance are provided as one 2D input of Y-Net; they are encoded and go through GCNs to account for neighbor layout partitions. Current map, derived from RS-GCN, becomes the second input. Final IR-drop map is extracted from the decoder. Experiments demonstrate that Y-Net, in conjunction with RS-GCN for current extraction, takes 2.5% of runtime from popular commercial solution with 15% prediction inaccuracy.

Interpolation is used to approximate the timing parameters of logic cells not specified in timing tables. Bilinear interpolation has been taken for granted in the industry, but the error increases as the nonlinearity of the timing parameters increases. In this article, we propose machine learning (ML)-based interpolation to obtain more accurate timing parameters. Recurrent convolutional neural network (R-CNN) is employed and various ranges of table entries form a sequence of input data, in which the recurrent network allows them to influence the interpolation. In addition, variational autoencoder (VAE) is used to capture the distribution feature of the table. ML interpolation is parallelized in GPU to minimize the runtime overhead from numerous arithmetic operations. Experimental results demonstrate that ML interpolation reduces timing parameter error by 19.7% and path delay error by 3.4% compared to bilinear interpolation at the cost of 13% runtime overhead.

Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Decaps become more complex these days while a number of metal layers are used for internal connection, thereby starting to manifest themselves as routing blockage. Postplacement decap insertion with both IR-drop violations and routing design rule violations (DRVs) being taken into account is addressed for the first time. Local cell relocation is performed to reduce the number of decaps in the actual decap insertion step. U-Net integrated with a graph convolutional network (GCN) is introduced to predict the DRV probability, which drives decap insertion. The problem of decap insertion is then formulated as mixed integer quadratically constrained programming (MIQCP) and a heuristic algorithm is presented for practical application. Experiments with a few test circuits demonstrate that the increase in routing DRV is reduced by 26% on average with no IR-drop violations, compared to conventional methods that do not explicitly consider DRVs. This brings a 60% reduction in routing runtime and a 33% improvement in total negative slack (TNS).

Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Their design becomes more complex and uses higher metal layers, thereby starting to manifest themselves as routing blockage. Post-placement decap insertion, with a goal of minimizing both IR-drop violations and routing design rule violations (DRVs), is addressed for the first time. U-Net with graph convolutional network is introduced to predict routing DRV penalty. The decap insertion problem is formulated and a heuristic algorithm is presented. Experiments with a few test circuits demonstrate that DRVs are reduced by 16% on average with no IR-drop violations, compared to a conventional method which does not explicitly consider DRVs. This results in 48% reduction in routing runtime and 23% improvement in total negative slack.

Power distribution network (PDN) consumes many routing resources to satisfy IR-drop constraints. With the increasing IR drop and the decreasing metal tracks in recent technology, the design of PDN becomes very important for circuit routing. In this paper, post-placement PDN optimization is proposed for routability enhancement. For a given regular PDN, we iteratively remove partial straps that have a small impact on IR-drop while improving routing overflow. Hierarchical layout-aware graph convolutional network (HLA-GCN) is introduced to find the candidate areas for strap removal, and one area is selected based on scoring. This process is applied twice to reduce the candidates for strap removal, and one strap is finally chosen after identifying the actual impact on IR-drop and routing congestion. This method is enabled by fast incremental IR-drop analysis using PDN-GCN, which classifies nodes with voltage change to update only those nodes in the modified nodal analysis. Experimental results address that the proposed method reduces routing overflow by 16% in an acceptable time, where IR-drop values are updated quickly with high accuracy of less than 2% error.

Airgap formed in intermetal dielectric (IMD) reduces coupling capacitance, and thus can be utilized for timing optimization. Metal layers with airgap are limited due to high cost of airgap formation. Layer reassignment is to relocate some timing critical wires in nonairgap layers to airgap layers while noncritical wires in airgap layers are reassigned to nonairgap layers. Airgap insertion is to determine the amount of airgaps that are inserted for each critical wires in airgap layers. The two problems are solved in unified fashion with a goal of maximizing setup total negative slack (TNS) while satisfying hold constraints and design rules. They can be formulated as mixed-integer quadratically constrained programming (MIQCP). So, for practical application, a heuristic algorithm is presented and is experimentally compared to MIQCP with small examples. The experiments demonstrate that setup TNS and setup worst negative slack (WNS) are improved by 37% and 8%, respectively; they are improved by 26% and 5% with a simple-minded approach. The algorithm is also parallelized for application to larger circuits; runtime is decreased by 69% with eight threads.

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. In this article, we propose two routability optimization methods to implement designs even with very low (or high) aspect ratio and high area utilization. First, we find the best assignment of non-uniform placement utilization through convolutional neural network model, and cell placement is performed while respecting the placement utilization. This allows many cells to be spread out over the entire design rather than being centered. The experiments show that most overflows of 16.5% occurring in cell placement are removed with 23.1% reduction in wire length; this is the result of further improving overflow of 9.8% compared to a conventional method. In the second, some flip-flops are selectively stacked to reduce the routing resources used for clock routing. U-Net model is built with graph attention network to predict the congestion after clock-tree synthesis, and the flip-flops in highly congested areas are selected for stacking. The proposed method improves the overflows, which occurs after clock-tree synthesis, by 22.1%.

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. We observe that non-uniform setting of utilization target greatly helps in these designs, specifically low utilization in the center and gradually higher utilization toward the ends. We introduce a convolutional neural network (CNN) model to predict the setting of utilization target values. Experiments indicate that routing congestion overflows are reduced by 29% on average of test designs with 40% reduction in wirelength.

Airgap is an intentional void formed in inter-metal dielectric (IMD). It brings about reduced coupling capacitance, and so can be used to improve circuit timing. Airgap can be utilized in a limited number of metal layers due to its high process cost. For given airgap layers, two problems should be addressed to insert airgap: relocate some metal segments in non-airgap layers into airgap layers (called layer reassignment) and determine the amount of airgap for each metal segment in airgap layers (airgap insertion). Two problems are solved together in this paper with a goal of maximizing setup total negative slack (TNS) while assuring no hold violations. It is formulated as mixed integer quadratically constrained programming (MIQCP); heuristic algorithm is proposed for practical application and its performance against MIQCP is experimentally assessed using small test circuits. Experiments demonstrate that TNS and WNS are improved by 35% and 10%, respectively, while simple minded approach achieves 6% and 4% less improvements compared to the proposed method.