This paper presents a multi-band front-end module (FEM) with a built-in transmit/receive (T/R) switch in 28 nm standard CMOS technology for 5G NR communication. A T/R switch topology is proposed to separate the design processes of the power amplifier (PA) and the low noise amplifier (LNA), which reduces the insertion loss in Tx mode caused by the T/R switch. To enable cover the all 5G NR bands at 28 GHz and 39 GHz, a four-coupled inductor-based reconfigurable inductor is used to shift the operational band in the interstage matching network of the low noise amplifier (LNA) and power amplifier (PA). Identical signal paths are used for both the LNA and PA. The FEM consists of a two-stage pseudo-differential PA with a cascade output stage to obtain high output power, a single-end LNA with two-stage cascade to achieve high power gain, and a compact and relatively low insertion loss T/R switch. The measured OP1dB and PAEOP1dB in Tx mode are 17.42 dBm and 16.36%, respectively. The measured NFmin in Rx mode is 5.65 dB. A 64-QAM 600 MSym/s single-carrier was measured in Tx mode.

This work presents a linearized Ka-band heterodyne receiver for millimeter-wave phased-array systems with high linearity requirement. A folded class-AB inductive peaking mixer and a two-stage magnetic self-cancellation-based load-pull interstage matching Intermediate-frequency (IF) amplifier are proposed to improve the linearity of input and output 1-dB compression point, respectively. The proposed receiver is implemented in 65 nm CMOS technology and its core area is 0.7 mm2. The measured input 1-dB compression point (IP1dB) is −10.9dBm and the output 1-dB compression point (OP1dB) is 7.1 dBm, with noise Figure (NF) of 10.1 dB at center frequency. To the best knowledge of the authors, the proposed RX achieves the highest IP1dBand OP1dBamong all the listed publications in silicon technology. The power consumption of the receiver including LO path is 119mW.

A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm2from a 1-V supply. The 2.25-$\mu \text{A}$hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40-$\mu \text{W}$XO features a low-frequency inaccuracy of 4 ppm/V. The 40-$\mu \text{A}$relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation.

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18-24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%-4.28%/V and temperature coefficients (TCs) of 22-32 ppm/°C across multiple chips has a power dissipation around 2.25 μW from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/√Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4-100 ms.