Memristors have recently shown significant promise in designing memory and logic subsystems. A 2D-crossbar architecture built with memristor arrays provides a convenient platform for storing multivalued memory states by utilizing the analog variation of current-induced resistance through these cells. The integration of CMOS components with non-CMOS memristor cells further enhances the scope of their applications to various complex system designs. However, present-day memristors by virtue of their inherent structure are prone to various manufacturing defects and sensitive to operational modalities. Existing techniques for testing memristor arrays are either ad hoc in nature or suited for application-specific designs with little concern for optimizing test time. In this work, we envisage a 2-D memristor crossbar as a network and identify certain paths that are suitable for fault sensitization. For full-size square and rectangular memristive crossbars, the proposed method optimizes test time using a path-based technique guided by maximum matching in bipartite graphs. An integer linear programming (ILP) formulation is then used to solve the problem for a general crossbar, either full or incomplete. Simulation results with LTspice demonstrate the effectiveness and superiority of the method to the prior art in terms of test time and fault coverage.

Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.