Mohammad Afzal 0001

dblp:256/6193-1 · DBLP profile ↗
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5ranked-venue papers
4as first author
3since 2021 · last 2026
0000-0002-6173-3959ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 4 first-author · 3 since 2021Theory of computation · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2026 Formal Reasoning About Confidence and Automated Verification of Neural Networks
abstract
Abstract In the last decade, a large body of work has emerged on robustness of neural networks, i.e., checking if the decision remains unchanged when the input is slightly perturbed. However, most of these approaches ignore the confidence of a neural network on its output. In this work, we aim to develop a generalized framework for formally reasoning about the confidence along with robustness in neural networks. We propose a simple yet expressive grammar that captures various confidence-based specifications. We develop a novel and unified technique to verify all instances of the grammar in a homogeneous way, viz., by adding a few additional layers to the neural network, which enables the use any state-of-the-art neural network verification tool. We perform an extensive experimental evaluation over a large suite of 8870 benchmarks, where the largest network has 138M parameters, and show that this outperforms ad-hoc encoding approaches by a significant margin.
Mohammad Afzal 0001, S. Akshay 0001, Blaise Genest, Ashutosh Gupta 0001
FM (1)1
2024 Unifying Syntactic and Semantic Abstractions for Deep Neural Networks
Sanaa Siddiqui, Diganta Mukhopadhyay, Mohammad Afzal 0001, Hrishikesh Karmarkar, Kumar Madhukar
FMICS3
2023 Using Counterexamples to Improve Robustness Verification in Neural Networks
Mohammad Afzal 0001, Ashutosh Gupta 0001, S. Akshay 0001
ATVA (1)1
2020 VeriAbs : Verification by Abstraction and Test Generation (Competition Contribution)
abstract
Abstract VeriAbs is a strategy selection based reachability verifier for C code. It analyzes the structure of loops, and intervals of inputs to choose one of the four verification strategies implemented in VeriAbs. In this paper, we present VeriAbs version 1.4 with updates in three strategies. We add an array verification technique called full-program induction, and enhance the existing techniques of loop pruning, k-path interval analysis, and disjunctive loop summarization. These changes have improved the verification of programs with arrays, and unstructured loops and unstructured control flows.
Mohammad Afzal 0001, Supratik Chakraborty, Avriti Chauhan, Bharti Chimdyalwar, Priyanka Darke, Ashutosh Gupta 0001, Shrawan Kumar 0001, Charles Babu M, Divyesh Unadkat, R. Venkatesh 0001
TACAS (2)1
2019 VeriAbs : Verification by Abstraction and Test Generation
abstract
Verification of programs continues to be a challenge and no single known technique succeeds on all programs. In this paper we present VeriAbs, a reachability verifier for C programs that incorporates a portfolio of techniques implemented as four strategies, where each strategy is a set of techniques applied in a specific sequence. It selects a strategy based on the kind of loops in the program. We analysed the effectiveness of the implemented strategies on the 3831 verification tasks from the ReachSafety category of the 8th International Competition on Software Verification (SV-COMP) 2019 and found that although classic techniques - explicit state model checking and bounded model checking, succeed on a majority of the programs, a wide range of further techniques are required to analyse the rest. A screencast of the tool is available at https://youtu.be/Hzh3PPiODwk.
Mohammad Afzal 0001, Asia A, Avriti Chauhan, Bharti Chimdyalwar, Priyanka Darke, Advaita Datar, Shrawan Kumar 0001, R. Venkatesh 0001
ASE1