VLDB 2026 Research / reviewers in the wild / expert
Yaroslav Sovyn
dblp:256/7243
· DBLP profile ↗
2ranked-venue papers
2as first author
1since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 1 · 1 first-authorSecurity and privacy · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 83% Hardware security and side channels · 17% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cryptographic primitives and cryptanalysis › cryptographic implementation
bitslice implementation |
0.7 | 1 | 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions · IEEE Trans. Inf. Forensics Secur. 2023 |
Cryptographic primitives and cryptanalysis
block cipher |
0.7 | 1 | 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions · IEEE Trans. Inf. Forensics Secur. 2023 |
Cryptographic primitives and cryptanalysis › cryptographic implementation
s-box implementation |
0.7 | 1 | 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions · IEEE Trans. Inf. Forensics Secur. 2023 |
Processor architecture and microarchitecture
instruction set architecture |
0.7 | 1 | 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions · IEEE Trans. Inf. Forensics Secur. 2023 |
Processor architecture and microarchitecture › SIMD
SIMD instructions |
0.7 | 1 | 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions · IEEE Trans. Inf. Forensics Secur. 2023 |
Hardware security and side channels
side-channel attack |
0.2 | 1 | 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions · IEEE Trans. Inf. Forensics Secur. 2023 |
Hardware security and side channels › side-channel attack
timing side channel |
0.2 | 1 | 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions · IEEE Trans. Inf. Forensics Secur. 2023 |
Methods — techniques the papers use, named apart from their topics
ternary logic · 1.3heuristic minimization · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD InstructionsabstractThe article is devoted to software bitsliced implementation of randomly generated$8\times 8$S-Box block ciphers, focused on the use of logical SIMD instructions from the SSE, AVX and AVX-512 extensions in ×86-64 processors. A heuristic algorithm for minimizing non-algebraic S-Boxes in three logical bases is proposed: universal—based on logical instructions AND, OR, XOR, NOT, which allows implementation on any 8/16/32/ 64-bit processors; extended—based on the instructions AND, OR, XOR, NOT, AND-NOT, which allows implementation on ×86-64 processors; ternary—based on ternary logic instructions, for implementation on ×86-64 processors with AVX-512 support. On average, bitsliced representations of non-algebraic S-Boxes in these logical bases require 400/380/200 logical instructions, respectively. The performance of bitsliced implementations of the S-Box cipher “Kalyna” using logical instructions SSE/AVX/ AVX-512 for the Intel Xeon Skylake-SP processor was measured. A fast alternative—non-bitsliced approach to the bytesliced SubBytes operation based on the AVX-512VBMI extension, resistant to timing and cache attacks—is proposed. Yaroslav Sovyn, Volodymyr Khoma, Michal Podpora |
IEEE Trans. Inf. Forensics Secur. | 1 |
| 2020 | Comparison of Three CPU-Core Families for IoT Applications in Terms of Security and Performance of AES-GCMabstractThis article describes the implementation of the AES-GCM for IoT-oriented low-end 8/16/32-bit general-purpose processors. Although various aspects of implementations of the AES-GCM for high-end processors and hardware were examined in detail, the low-end processors to a lesser extent. This article estimates the speed and memory demand for various approaches to ensuring resistance to attacks, such as timing analysis and simple power analysis by ensuring the constant algorithm execution time. A particular attention is paid to the low-level multiplication implementation in GF (2128) for each architecture as a key galois/counter mode operation, because low-end processors do not have ready-made instructions for carry-less multiplication. For each AVR/MSP430/ARM Cortex-M3 processor core, a constant time implementation of carry-less multiplication is proposed, the performance of which approaches the Not Constant Time algorithm. Yaroslav Sovyn, Volodymyr Khoma, Michal Podpora |
IEEE Internet Things J. | 1 |