Implantable biomedical circuits offer wide applications including the treatment of neurological disorders. To ensure reliability in terms of ESD (Electrostatic discharge) damage from fabrication, packaging, and user handling, ESD protection is required to protect the core circuit from any damage. A complete closed-loop neuromodulation SoC with on-site recording and digital core coupled with the cost necessitates the design to be implemented in a 65nm CMOS technology. Custom ESD protection has to be incorporated since the foundry-provided ESD cannot handle the high voltages required for faithful current stimulations. While existing stimulator designs in 65nm CMOS use implicit diodes of the driver stage as part of ESD protection, we show that this leads to coupling of the ESD design with the driver design, leading to suboptimal area and possible failure cases due to stress. This work proposes a 10 V compliant stimulator with an ESD protection circuit in± a 65 nm CMOS process verified for the HBM model using post-layout TLP simulations. This work also provides insights and details on the decoupling of the ESD design from the stimulator driver design to realize a low-footprint device.

The development of implantable on-chip machine learning (ML) classifiers has opened new possibilities for treating neurological disorders through closed-loop responsive neurostimulation. However, implementing ML algorithms in hardware requires optimizing area and power efficiency while maintaining low processing latency. Additionally, non-idealities in the analog front-end can significantly affect the classifier’s real-time performance. This paper explores the influence of these effects and proposes a gain correction technique to be implemented during the training phase, thereby enhancing the system’s robustness. A 16-channel time-division multiplexed (TDM) digital backend system was designed in 65nm CMOS technology. The designed System on Chip (SoC) relies on three spectral features from distinct physiological frequency bands, extracted via a FIR filter, and was tested on EEG data from the CHB-MIT scalp EEG database. The proposed implementation across process corners achieved a sensitivity of 95.4%, specificity of 93.3%, accuracy of 94.4% and the energy efficiency of the digital system was 24.126 µJ/classification at 0.9V.

Bio-inspired axonal and dendritic delay-based spiking neural network algorithms perform spatiotemporal pattern recognition efficiently within feed-forward networks, making complex and suboptimal recurrent neural network structures unnecessary. Including trainable dendritic or axonal delays in feed-forward neural networks reduces neural network complexity and improves classification performance significantly. However, generating tunable low-power hardware spike delays of the biological timescale (few μs to ms ) without adding an extra penalty on the area has been challenging over the years. We present a novel band-to-band tunneling-based tunable delay element for spiking neural network hardware. The proposed low-power core delay element capable of providing spike delays of up to 0.4 ms (without explicit capacitance) consumes an area of 50 μm2in GF45RFSOI technology with a peak power of 320 nW, which is the lowest among state-of-the-art spike delay generation circuits. Moreover, the order of the spike delay can be extended to 25 ms by adding an explicit on-chip capacitance of 500 fF.

This work proposes a neuromodulation-inspired spiking neural network using a ReRAM memory. A stashing-merging algorithm is realized to mimic the inherent neuromodulation in humans. While traditional pruning methods remove redundant parts of the network, stashing excludes well-trained neurons while training and restores all neurons at the end of training. This approach exhibits energy-efficient training in the context of a spiking neural network (SNN) since well-trained neurons can be easily identified using the spike count. The idea is validated using a ReRAM-based SNN with 10 conductance levels and performs close to a traditional artificial neural network (ANN) on an MNIST classification workload.

Resistive random access memory (ReRAM) based analog in-memory-compute (IMC) coupled with spiking neural networks (SNN) offers a promising solution to implement efficient matrix multiplication. This work presents an ARM Cortex-based ReRAM IMC for rapid SNN workload evaluation. While the software flexibility and the scheduling are provided by the ARM processing system (PS), the programmable logic (PL) provides a scalable interface to the ReRAM array through mixed-signal digital-to-analog converters (DAC). A prototype system is presented using a Zynq 7000 SoC comprising an ARM PS and PL infrastructure. Custom 8x8 ReRAM array along with row and column DACs and leaky-integrate and fire (LIF) neurons are implemented to realize the end-to-end system. A use-case of a stashing-based MNIST classification task is demonstrated using the prototype system.

Combinatorial optimization problems (COPs), when addressed using traditional von Neumann computers, demand significant computational power and substantial area as problem dimensionality increases. Hardware-based solvers, particularly those employing coupled oscillator networks to mimic Ising machines, have been explored as alternatives. However, conventional CMOS-based solutions face limitations in terms of power consumption and area. In this work, we propose a low-power 8-node oscillatory neural network using a band-to-band-tunneling-based ring oscillator in GF45RFSOI technology. This ultra-low power and low-area design efficiently solves COPs without an external perturbation signal. We use the intrinsic noise of BTBT-based oscillators to augment the phase synchronization among the coupled oscillators. The proposed system allows configurable all-to-all connectivity between ring oscillator nodes through cross-coupled capacitors. We demonstrate the system’s efficacy in solving multiple vector graph coloring problems, achieving an average power consumption of 0.93 nW (105× lower than state-of-the-art) per oscillator with a supply voltage of 1.8 V.

On-chip training at the edge becomes a primary requisite for real-time and security-sensitive artificial neural network (ANN) applications. In-memory computation (IMC) techniques have been proposed to facilitate data-intensive computational operations in ANNs. IMC-based multiply-accumulate (MAC) accelerates ANN training but suffers from significant communication overhead between the MAC engine and the off-chip storage for the intermediate data. This article proposes an analog temporary on-chip memory (ATOM) to store this intermediate data during ANN training. The ANN training architecture with the proposed ATOM has two significant advantages. First, the energy required to store intermediate data is scaled down by \(\sim\) 40 \(\times\) due to the on-chip and analog nature of the memory. Second, the proposed architecture avoids power and area-consuming analog-to-digital converters (ADCs) between neural network stages. The ATOM cell measurements are carried out from 20 fabricated chips, and the impact of ATOM characteristics on ANN system performance accuracy is analyzed. This article shows significant latency improvement of \(\sim\) 9 \(\times\) and area savings of \(\sim\) 5 \(\times\) for intermediate data storage compared to the on-chip SRAM during ANN training’s forward and backward pass operations. An improvement in the area and latency will be beneficial to instrument the area- and energy-efficient hardware system for on-chip ANN applications.

Brain-machine interface (BMI) devices have emerged as a promising solution for a wide range of neural disorders ranging from depression, epilepsy, and Parkinson’s disease. Implantable neural recording circuits to realize BMI devices mostly rely on off-chip computation either to train a classifier or train and infer off-chip. This results in the need for efficient off-chip data transmission with constrained power budgets. This work delves into on-chip compression of neural signals for energy-efficient data transmission. We provide a comparative study of two hardware-efficient algorithms: Compressed Hadamard Transform (CHT) and Compressed Sensing (CS), in the context of high-density neural data compression. The CHT and CS compression engines along with the data interface and stimulator digital core were implemented on a 65nm CMOS technology and compared for their area, power, and reconstruction error performance. We conclude that the CHT approach is 6.6% power and 6.5% more area efficient while still providing better reconstruction compared to CS technique.

Efficient and compact neurons with low power consumption are crucial when designing large-scale spiking neural networks (SNNs) for hardware implementation. Many architectures in the literature showcase different spike patterns associated with biological neurons. However, using bulky capacitors to generate the different time constants related to complex neuron patterns makes these circuits area inefficient. This paper presents a band-to-band-tunneling (BTBT) based energy-efficient and compact neuron capable of producing various spike patterns. The BTBT region’s extremely low current enables different time constants while eliminating the need of bulky capacitors. The circuit is based on the Izhikevich neuron model. The proposed circuit is designed in Silicon on Insulator technology to exhibit important firing patterns observed in the biological cortex, viz. regular spiking, fast-spiking, and chattering, and it is fine-tuned for efficient operation at low subthreshold voltages. This circuit utilizes only 129 μm2area and consumes only 6.7 fJ energy per spike ( approximately 40% lower area and energy per spike than state-of-the-art multi-mode neurons) in G45RFSOI technology.

Solving classification problems using Spiking Neural Networks (SNNs) involves determining the most active neuron in the output layer. Scalable, low-power and low-area hardware solutions for such decision-making are vital for neuromorphic edge applications to meet power and space constraints. In this work, we propose a low-power, compact Winner-Take-All (WTA) circuit, a multi-input multi-output dynamic threshold comparator that simultaneously compares multiple analog voltage inputs and provides a one-hot-encoded digital output vector indicating the result of the classification. The design eliminates the need for cascading and a dedicated feedback circuit. A spike integrator stage captures the temporal activity of a set of neurons, and these activities are compared and digitized by the proposed WTA comparator stage. The proposed WTA designed in GF45RFSOI technology, exhibits self-excitation and global-inhibition properties, offers scalability, consumes 44% less power (140 nW ) and occupies a 40% lower area (166 μm2), compared to state-of-the-art.

This work presents a continuous-time delta-sigma modulator (CTDSM) deploying an experimentally demonstrated band-to-band-tunelling (BTBT) SOI MOSFET-based loop filter. With a compact, low-pass filter circuit and extremely low current in the BTBT regime, a loop filter implementation will provide optimality in terms of area and power performance. In literature for moderate-resolution CTDSMs, traditional loop filters are implemented with either fully passive, active, or hybrid integrators. These designs have a tight tradeoff in terms of area and power. The passive integrators have optimal power but suboptimal area, while the active integrators have optimal area and sub-optimal power consumption. The proposed work tries to break this tradeoff using BTBT regime loop filters. The CTDSM was designed in a GF45RFSOI technology and achieves a peak SNR/SNDR of 48.41 dB/47.94 dB for a 5 kHz bandwidth. The power consumption is 76.3 nW, with an area of 102.7 μm2— more than 100x area reduction over previous state-of-the-art moderate-precision CTDSM designs. This makes the proposed CTDSM extremely compact and power-efficient compared to traditional state-of-the-art moderate-resolution DSMs.

This work proposes an all-digital on-chip digital Frequency measuring system (FMS) that is intended to replace conventional low-resolution measuring instruments. The method of measurement is a two-step process with a coarse estimate followed by a fine resolution frequency estimation from three DFT samples using the Candan method. We describe the design, and performance evaluation, as a high-resolution rapid frequency measurement system, particularly for high-precision MEMS applications. The proposed FMS has been synthesized, implemented and verified on a Xilinx ZYNQ XC7Z020-1CLG400C SoC. The ASIC implementation of the SoC on a 65nm CMOS technology reveals that the design consumes 120 mW power at a 100 MHz clock while providing sub-5 ppm resolution with a readout time of 5.7 μs, suitable for MEMS applications with bandwidth up to 10 MHz.

On-chip machine learning classifiers (ML) can be used in implantable neuromodulation SoCs to detect the onset of seizures and suppress disease symptoms through Responsive Neurostimulation (RNS). While ML classifiers can be very effective in predicting the clinical onset of a seizure, they have a tight power, area and latency budget. This paper presents the implementation of an energy-efficient Neural Tree classifier hardware for seizure prediction. The proposed implementation is easily scalable and can also be used for the prediction of other neural disorders. The Neural Tree classifier is implemented on 65nm CMOS technology and it uses a maximum of 5 Spectral features from 16 channels to make a prediction. The classifier is trained on human electroencephalography (EEG) data from the CHB-MIT scalp EEG Database. The proposed implementation achieved a sensitivity of 97.9%, a specificity of 86.5%, and an energy efficiency of 0.16 μJ/classification with a total power consumption of 8.2 μW at 1.2 V supply voltage.

Liquid State Machine (LSM) is a brain-inspired neural network architecture for solving temporal classification problems like speech recognition. The simple structure of LSM with a reservoir and single-layer classifier is attractive from a hardware implementation perspective. When the LSM is considered for low-power hardware implementation in real-world command word recognition tasks, challenges like nonidealities in sensor filter response and ambient noise become critical concerns. In this work, we evaluate the performance of LSM based on two aspects (1) ambient noise and (2) sensor/preprocessing circuit nonidealities. For Ambient noise, we use additive white gaussian noise (AWGN) and ambient noise using the iNoise Indian Noise dataset that covers various natural indoor, outdoor, and travel-related environmental sounds. To understand the impact of input hardware nonidealities, we analyzed the impact of the audio preprocessing filter's quality factor, order, center frequency variations, and output nonlinearity on LSM performance. We use the spoken digits classification in the TI-46 dataset. This paper's findings present design guidelines for the system designers intending to use liquid-state machines for speech classification tasks. In terms of filter design, first, there is a broad Q, order space for filter design where performance is high. We use the hardware-friendly parallel 4th order Butterworth bandpass filter model to provide a baseline 98% accuracy in speech classification tasks. Second, the performance of LSM degrades proportionally to the variation in the center frequency of the bandpass filters in the filter bank. Third, nonlinearity with the third-order harmonic of 50 dBc can be tolerated. Regarding ambient noise, our study shows that a 40 dB SNR for AWGN is sufficient for ideal performance. Second, the best case of “home” noise leads to a performance of 91.4%. Outdoor and travel noise reduce the classification performance to 78.8% and 62.4%, respectively. However, ideal performance is recovered if the signal to noise ratio (SNR) is increased, particularly by 10 dB in indoor conditions and 30 dB in outdoor conditions. Thus, our study presents an engineering evaluation for real-world spoken digit recognition using LSMs.

Resistive RAM (RRAM) devices are compact and easy to fabricate with electrical inputs-based switching. Conductive-Bridge RRAM (CBRAM) is being developed to meet retention, endurance and reliability specifications by GlobalFoundries for typical 1-bit per cell digital storage. However, filamentary growth and rupture produce variability, and the resistance states can often span multiple orders. We explore whether digital-storage-focused CBRAM can support analog current readout-based Multiply-and-Accumulate operations in artificial neural network (ANN) applications. We explore the 2T-1R bit cell to tune the mean HRS/LRS ratio and to control the variability in HRS and LRS readouts. We use experimental CBRAM data and GlobalFoundries' 22FDX platform and demonstrate > 2 × reduction in HRS and LRS logscale variability and > 10 × higher HRS/LRS ratio for the 2T-1R bit cell. The strategy is successfully tested for two datasets – the simpler MNIST and the more complex FMNIST using system-level modeling of non-idealities like weight quantization, HRS/LRS ratio, and variability in the readout of each bit-cell. Such bit-cell design principles have general utility in exploiting variability-prone characteristics of emerging memories for excellent application-level performance.

Neurostimulation devices have emerged as a promising therapeutic solution for a wide range of neural disorders ranging from depression, epilepsy and Parkinson's. This paper delves into the data security aspect of such devices. The work provides a comparative study of the two popular ciphers namely, DES-64 and AES-128 in the context of neurostimulators. The two cipher algorithms are implemented on an FPGA and verified functionally for the stimulation functionality. The DES-64 and AES-128 decryption engines along with the data interface and stimulator digital core were implemented on a 65nm CMOS technology using two MOS flavors namely low-VT and regular-VT low-leakage devices. Post-layout simulation results show that the low-VT design outperforms the regular-VT design for data rates above 1Mbps. Finally, simulation results show that the AES-128 consumes 28% extra power compared to DES-64, however with a superior data security margin.

The design of$\Delta \Sigma $modulators for multichannel biomedical applications introduces challenges with high density and very low power consumption. While possible solutions in the form of VCO and passive integrator-based$\Delta \Sigma $modulators have been reported, these modulators suffer from limited resolution. Hybrid$\Delta \Sigma $modulators provide an excellent tradeoff between area, power, and achievable resolution compared to the counterpart active and passive integrator$\Delta \Sigma $modulators. This work explores hybrid continuous-time delta–sigma modulator (CTDSM) architectures for multichannel biomedical applications, operating with a single clock phase. To alleviate the high power consumption of the active integrators in the CTDSM, an auxiliary digital-to-analog converter (DAC)-based and a passive$RC$front-end-based hybrid CTDSMs are proposed. Through a detailed analysis and performance comparison, we demonstrate that the two proposed hybrid architectures exhibit the classical area–power tradeoff for a target resolution. We demonstrate the designs in standard 180-nm mixed-mode CMOS technology for biomedical bandwidth. Measurement results show that the auxiliary DAC and the PRC-FE-based hybrid CTDSMs achieve an SNDR and DR of 65.18 and 68.3 dB and 66.85 and 71.1 dB while consuming 845- and 730-nW power and achieving an FoM of 28.48 and 20.3 fJ/conv, respectively, ideal for multichannel biomedical applications.In vitroandin vivomeasurements are also performed to validate the proposed hybrid CTDSM designs.

Resonant MEMS sensors have potential of providing highly precise measurements. The accurate processing of the output relies on precise frequency estimation techniques especially in the context of portable sensors for particulate matter. This paper investigates five commonly used single-tone frequency estimation techniques (3-point DFT interpolation, parabolic interpolation of periodogram peak, Prony's method, modified Pisarenko and zero crossing method) with respect to the estimation accuracy, memory requirement and computational complexity. The effect of noise and harmonics on estimation accuracy of these five techniques are analyzed and validated through simulation. The experimental data is acquired from a resonant MEMS sensor with a center frequency of 3.15 MHz. The output is sampled at 100MS/s using a 12-bit ADC. These five techniques are applied to the various data sets acquired from an experimental setup. The comparison results along with the analysis are presented.

In this brief, a 300-mV, auto shutdown comparator based on a novel clock gating network is proposed. The proposed auto shutdown comparator is further employed to realize a compact, ultralow power continuous-time ΔΣ modulator (CTDSM) with a 300-mV supply voltage for multichannel sensing and biomedical applications. The design was fabricated in standard mixed-mode 180-nm CMOS process. Measurement results show that the CTDSM achieves a peak SNDR of 54.81 dB and DR of 57.4 dB while consuming a core power of 1.76 μW at 300-mV supply voltage without the clock-gated comparator. With the clock-gated auto shutdown comparator, the CTDSM consumes a core power of only 220 nW thereby providing an eight times power saving. Moreover, the fabricated CTDSM occupies an extremely small area of 0.0464 mm2 with an energy efficiency of 24.5 fJ/conv making it the most compact and energy-efficient CTDSM reported till date among the moderate resolution CTDSMs. Furthermore, by increasing the supply voltage to 400 mV, the CTDSM features a peak SNDR of 58.56 dB and DR of 64.1 dB while consuming a core power of 410 nW and 29.61 fJ/conv.