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Qianlan Hu

dblp:258/3383 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0000-0002-5498-4135ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 64% Integrated circuit design · 36%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › DRAM › DRAM architecture
3D-stacked DRAM
0.912025
Scaled 3D-stacked 2T0C DRAM based on indium-tin-oxide transistors with long data retention and fast write speed of 10 ns · Sci. China Inf. Sci. 2025
Memory systems
DRAM
0.912025
Scaled 3D-stacked 2T0C DRAM based on indium-tin-oxide transistors with long data retention and fast write speed of 10 ns · Sci. China Inf. Sci. 2025
Memory systems
non-volatile memory
0.312025
Improvement with low operation voltage in ultrathin La-doped Hf0.5Zr0.5O2 ferroelectric capacitors · Sci. China Inf. Sci. 2025

Methods — techniques the papers use, named apart from their topics

la doping · 0.9hf0.5zr0.5o2 · 0.9
YearPublicationVenuePosition
2025 Improvement with low operation voltage in ultrathin La-doped Hf0.5Zr0.5O2 ferroelectric capacitors
Shiwei Yan, Tianyue Fu, Honggang Liu, Qianlan Hu, Yanqing Wu
Sci. China Inf. Sci.6
2025 Scaled 3D-stacked 2T0C DRAM based on indium-tin-oxide transistors with long data retention and fast write speed of 10 ns
Shenwu Zhu, Qianlan Hu, Chengru Gu, Shiwei Yan, Aocheng Qiu, Yanqing Wu
Sci. China Inf. Sci.2